3.3.3. DCache operation

When the DCache is enabled, it is searched when the processor performs a load or store. If the cache hits on a load, data is returned to the cache if the Cd bit is 1. If the cache read misses, the Cd bit is examined. The meaning of the values of the Cd bit are shown in Table 3.2

Table 3.2. Meaning of Cd bit values

Cd bit value



Cachable data area and protection unit enabled. A linefill of eight words is performed and the data is written into a randomly chosen segment of the DCache.


A single or multiple external access is performed and the cache is not updated.


Stores that hit in the cache update the cache line if the Cd bit is 1. Stores that miss the cache use the Cd and Bd bits to determine whether the write is buffered. A write miss is not loaded into the cache as a result of that miss.

Load and store multiples are broken up on 4KB boundaries (the minimum protection region size), allowing a protection check to be performed in case the Load Multiple (LDM) or Store Multiple (STM) crosses into a region with different protection properties.

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