5.2.1. Enabling the I-SRAM

You can enable the I-SRAM by setting bit 18 of the CP15 control register. You must use read-modify-write to access this register to preserve the contents of the bits not being modified. See Register 1, Control register for details of how to read and write the CP15 control register. When you have enabled the I-SRAM, all future ARM9E-S instruction fetches and data accesses to the I-SRAM address space cause the I-SRAM to be accessed.

Enabling the I-SRAM greatly increases the performance of the ARM946E-S because the majority of accesses to it can be performed with no stall cycles. Accessing the AHB however, can cause several stall cycles for each access.


You must take care to ensure that the I-SRAM is appropriately initialized before it is enabled and used to supply instructions to the ARM9E-S core. If the core tries to execute instructions from uninitialized I-SRAM, the behavior is unpredictable.

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