6.2.1. About the AHB

The AHB architecture is based on separate cycles for address and data (rather than separate clock phases, as in ASB). The address and control for an access are broadcast from the rising edge of HCLK in the cycle before the data is expected to be read or written. During this data cycle, the address and control for the next transfer are driven out. This leads to a fully pipelined address architecture.

When an access is in its data cycle, a slave can extend an access by driving the HREADY signal LOW. This stretches the current data cycle, and therefore the pipelined address and control for the next transfer is also stretched. This provides a system where all AHB masters and slaves sample HREADY on the rising edge of HCLK to determine whether an access has completed and a new address can be sampled or driven out.

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