6.2.4. Linefetch transfers

The ARM946E-S is optimized to run with both the ICache and DCache enabled. If a memory request (either instruction or data) to a cachable area misses in the cache the ARM946E-S performs a linefetch.

A linefetch transfer is shown in Figure 6.1.

Figure 6.1. Linefetch transfer

A linefetch is a fixed length burst of eight words. The start address of a linefetch is aligned to an eight-word boundary. The ARM946E-S asserts the bus request HBUSREQ until the arbiter grants the AHB bus (HGRANT asserted). The bus request is then negated. This allows optimum system performance as the arbiter can accurately predict the end of the defined length burst.

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