The ARM946E-S supports streaming of data and instructions (core execution is advanced during the linefetch). To allow for cache look-ups when crossing a cache line boundary the ARM946E-S must insert IDLE cycles onto the AHB bus. The effect of this is shown in Figure 6.2. It is assumed in Figure 6.2 that HGRANT is asserted throughout, and that the HCLK frequency is the same as CLK.