6.4.1. CLK to HCLK skew

The ARM946E-S drives out the AHB address on the rising edge of CLK when the HCLKEN input is TRUE. The AHB outputs therefore have output hold and delay values relative to CLK. However, these outputs are used in the AHB system where transfers are timed using HCLK. Similarly, inputs to the ARM946E-S are timed relative to HCLK but are sampled within the ARM946E-S with CLK. This leads to hold time issues, from CLK to HCLK on outputs, and from HCLK to CLK on inputs. In order to minimize this effect you must minimize the skew between HCLK and CLK.

Figure 6.6 shows the AHB clock relationships.

Figure 6.6. AHB clock relationships

Clock tree insertion at top level

Considering the skew issue in more detail, the ARM946E-S requires a clock tree to be inserted to allow an evenly distributed clock to be driven to all the registers in the design. The registers that drive out AHB outputs and sample AHB inputs are therefore timed off CLK at the bottom of the inserted clock tree and subject to the clock tree insertion delay. To maximize performance, when the ARM946E-S is embedded in an AHB system, the clock generation logic to produce HCLK must be constrained so that it matches the insertion delay of the clock tree within the ARM946E-S. You can achieve this using a clock tree insertion tool, if the clock tree is inserted for the ARM946E-S and the embedded system at the same time (top level insertion).

Figure 6.7 shows an example of an AHB slave connected to the ARM946E-S.

Figure 6.7. ARM946E-S CLK to AHB HCLK sampling

In Figure 6.7, the slave peripheral has an input setup and hold, and an output hold and valid time relative to HCLK. The ARM946E-S has an input setup and hold, and an output hold and valid time relative to CLK’, the clock at the bottom of the clock tree. You can use clock tree insertion to position HCLK to match CLK’ for optimal performance.

Hierarchical clock tree insertion

If you perform clock tree insertion on the ARM946E-S before it is embedded, you can add buffers on input data to match the clock tree so that the setup and hold is relative to the top-level CLK. This is guaranteed to be safe at the expense of extra buffers in the data input path.

The HCLK domain AHB peripherals must still meet the ARM946E-S input setup and hold requirements. As the ARM946E-S inputs and outputs are now relative to CLK, the outputs appear comparatively later by the value of the insertion delay. This ultimately leads to lower AHB performance.

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