8.3.1. Reset

The JTAG interface includes a state-machine controller (the TAP controller). To force the TAP controller into the correct state after power-up of the device you must apply a reset pulse to the DBGnTRST signal, or you must cycle the JTAG state machine through the TEST-LOGIC-RESET state. Before you can use the JTAG interface, you must drive DBGnTRST LOW, and then HIGH again. If you do not intend using the boundary scan interface, you can tie the DBGnTRST input permanently LOW.

Note

A clock on TCK is not necessary to reset the device.

The action of reset is as follows:

  1. Forces exit from debug state. The boundary scan chain cells do not intercept any of the signals passing between the external system and the core.

  2. The IDCODE instruction is selected. If the TAP controller is put into the SHIFT‑DR state and TCK is pulsed, the contents of the ID register are clocked out of TDO.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
Non-Confidential