8.6.5. Debug request

A debug request can take place through the EmbeddedICE-RT logic or by asserting the EDBGRQ signal. The request is synchronized and passed to the processor. Debugrequest takes priority over any pending interrupt. Following synchronization, the core enters debug state when the instruction at the execution stage of the pipeline has completely finished executing (when memory and write stages of the pipeline have completed). While waiting for the instruction to finish executing, no more instructions are issued to the Execute stage of the pipeline.

Note

If EDBGRQ is asserted while the processor is operating in monitor mode, the processor enters debug state as if operating in halt mode.

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