8.6.6. Actions of the ARM9E‑S in debug state

When the ARM9E‑S is in debug state, both memory interfaces indicate internal cycles. This ensures that the tightly-coupled SRAM within the ARM946E-S, and the AHB interface, are both quiescent, allowing the rest of the AHB system to ignore the ARM9E‑S and function as normal. Because the rest of the system continues operation, the ARM9E‑S ignores aborts and interrupts.

The nRESET signal must be held stable during debug. If the system applies reset to the ARM946E‑S (nRESET is driven LOW), the state of the ARM9E‑S changes without the knowledge of the debugger.

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