10.3.1. BIST control register

The CP15 register 15 BIST control register controls the operation of the SRAM memory BIST. Before initiating a BIST test, an MCR is first performed to the BIST control register to set up the size of the test and enable the SRAM to be tested. An additional MCR is required to initiate the test.

You can access the current status of a BIST test and result of a completed test by performing an MRC to the BIST control register. This returns flags to indicate that a test is:

In addition to returning the state for the size of the test memory array, having completed a BIST test, if you wish to use the memory array for functional operation you must first clear the BIST enable by writing to the BIST control register. You must then re-enable the memory array by writing to CP15 register 1.


Clearing the functional memory array enable when BIST is enabled prevents you from trying to run from cache or tightly coupled SRAM following a BIST test, without having first flushed the cache memory and reprogrammed the SRAM. This is necessary as the BIST algorithm corrupts all tested memory locations.

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