A.1. Timing diagrams

The timing diagrams in this section are:

Clock, reset and AHB enable timing parameters are shown in Figure A.1.

Figure A.1. Clock, reset, and AHB enable timing

AHB bus request and grant related timing parameters are shown in Figure A.2.

Figure A.2. AHB bus request and grant related timing

AHB bus master timing parameters are shown in Figure A.3.

Figure A.3. AHB bus master timing

Coprocessor interface timing parameters are shown in Figure A.4.

Figure A.4. Coprocessor interface timing

Debug interface timing parameters are shown in Figure A.5.

Figure A.5. Debug interface timing

JTAG interface timing parameters are shown inFigure A.6.

Figure A.6. JTAG interface timing

A combinatorial path timing parameter exists from the DBGSDOUT input to DBGTDO output. This is shown in Figure A.7.

Figure A.7. DBGSDOUT to DBGTDO timing

Exception and configuration timing parameters are shown in Figure A.8.

Figure A.8. Exception and configuration timing

The INTEST wrapper timing parameters are shown in Figure A.9.

Figure A.9. INTEST wrapper timing

The ETM interface timing parameters are shown in Figure A.10.

Figure A.10. ETM interface timing

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