A.2. AC timing parameter definitions

Table A.1 shows target AC parameters. All figures are expressed as percentages of the CLK period at maximum operating frequency.

Note

The figures quoted are relative to the rising clock edge after the clock skew for internal buffering has been added. Inputs given a 0% hold figure therefore require a positive hold relative to the top-level clock input. The amount of hold required is equivalent to the internal clock skew

Table A.1. Timing parameter definitions

Symbol

Parameter

Min

Max

Tcyc

CLK cycle time

100%

-

Tishen

HCLKEN input setup to rising CLK

85%

-

Tihhen

HCLKEN input hold from rising CLK

-

0%

Tisrst

HRESETn de-assertion input setup to rising CLK

90%

-

Tihrst

HRESETn de-assertion input hold from rising CLK

-

0%

Tovreq

Rising CLK to HBUSREQ valid

-

30%

Tohreq

HBUSREQ hold time from rising CLK

>0%

-

Tovlck

Rising CLK to HLOCK valid

-

30%

Tohlck

HLOCK hold time from rising CLK

>0%

-

Tisgnt

HGRANT input setup to rising CLK

40%

-

Tihgnt

HGRANT input hold from rising CLK

-

0%

Tovtr

Rising CLK to HTRANS[1:0] valid

-

30%

Tohtr

HTRANS[1:0] hold time from rising CLK

>0%

-

Tova

Rising CLK to HADDR[31:0] valid

-

30%

Toha

HADDR[31:0] hold time from rising CLK

>0%

-

Tovctl

Rising CLK to AHB control signals valid

-

30%

Tohctl

AHB control signals hold time from rising CLK

>0%

-

Tovwd

Rising CLK to HWDATA[31:0] valid

-

30%

Tohwd

HWDATA[31:0] hold time from rising CLK

>0%

-

Tisrdy

HREADY input setup to rising CLK

75%

-

Tihrdy

HREADY input hold from rising CLK

-

0%

Tisrsp

HRESP[1:0] input setup to rising CLK

50%

-

Tihrsp

HRESP[1:0] input hold from rising CLK

-

0%

Tisrd

HRDATA[31:0] input setup to rising CLK

40%

-

Tihrd

HRDATA[31:0] input hold from rising CLK

-

0%

Tovcpen

Rising CLK to CPCLKEN valid

-

30%

Tohcpen

CPCLKEN hold time from rising CLK

>0%

-

Tovcpid

Rising CLK to CPINSTR[31:0] valid

-

30%

Tohcpid

CPINSTR[31:0] hold time from rising CLK

>0%

-

Tovcpctl

Rising CLK to transaction control valid

-

30%

Tohcpctl

Transaction control hold time from rising CLK

>0%

-

Tiscphs

Coprocessor handshake input setup to rising CLK

50%

-

Tihcphs

Coprocessor handshake input hold from rising CLK

-

0%

Tovcplc

Rising CLK to CPLATECANCEL valid

-

30%

Tohcplc

CPLATECANCEL hold time from rising CLK

>0%

-

Tovcpps

Rising CLK to CPPASS valid

-

30%

Tohcpps

CPPASS hold time from rising CLK

>0%

-

Tovcprd

Rising CLK to CPDOUT[31:0] valid

-

30%

Tohcprd

CPDOUT[31:0] hold time from rising CLK

>0%

-

Tiscpwr

CPDIN[31:0] input setup to rising CLK

40%

-

Tihcpwr

CPDIN[31:0] input hold from rising CLK

-

0%

Tovdbgack

Rising CLK to DBGACK valid

-

60%

Tohdbgack

DBGACK hold time from rising CLK

>0%

-

Tovdbgrng

Rising CLK to DBGRNG[1:0] valid

-

60%

Tohdbgrng

DBGRNG[1:0] hold time from rising CLK

>0%

-

Tovdbgrqi

Rising CLK to DBGRQI valid

-

45%

Tohdbgrqi

DBGRQI hold time from rising CLK

>0%

-

Tovdbgstat

Rising CLK to DBGINSTREXEC valid

-

30%

Tohdbgstat

DBGINSTREXEC hold time from rising CLK

>0%

-

Tovdbgcomm

Rising CLK to comms channel outputs valid

-

30%

Tohdbgcomm

Comms channel outputs hold time from rising CLK

>0%

-

Tisdbgin

Debug inputs input setup to rising CLK

30%

-

Tihdbgin

Debug inputs input hold from rising CLK

-

0%

Tisiebkpt

DBGIEBKPT input setup to rising CLK

20%

-

Tihiebkpt

DBGIEBKPT input hold from rising CLK

-

0%

Tisdewpt

DBGDEWPT input setup to rising CLK

20%

-

Tihdewpt

DBGDEWPT input hold from rising CLK

-

0%

Tovdbgsm

Rising CLK to debug state valid

-

30%

Tohdbgsm

Debug state hold time from rising CLK

>0%

-

Tovtdoen

Rising CLK to DBGnTDOEN valid

-

40%

Tohtdoen

DBGnTDOEN hold time from rising CLK

>0%

-

Tovsdin

Rising CLK to DBGSDIN valid

-

20%

Tohsdin

DBGSDIN hold time from rising CLK

>0%

-

Tovtdo

Rising CLK to DBGTDO valid

-

65%

Tohtdo

DBGTDO hold time from rising CLK

>0%

-

Tisntrst

DBGnTRST de-asserted input setup to rising CLK

35%

-

Tihntrst

DBGnTRST input hold from rising CLK

-

0%

Tistdi

Tap state control input setup to rising CLK

25%

-

Tihtdi

Tap state control input hold from rising CLK

-

0%

Tistcken

DBGTCKEN input setup to rising CLK

50%

-

Tihtcken

DBGTCKEN input hold from rising CLK

-

0%

Tistapid

TAPID[31:0] input setup to rising CLK

20%

-

Tihtapid

TAPID[31:0] input hold from rising CLK

-

0%

Tdsd

DBGTDO delay from DBGSDOUTBS changing

-

30%

Tdsh

DBGTDO hold time from DBGSDOUTBS changing

>0%

-

Tovbigend

Rising CLK to BIGENDOUT valid

-

30%

Tohbigend

BIGENDOUT hold time from rising CLK

>0%

-

Tisint

Interrupt input setup to rising CLK

15%

-

Tihint

Interrupt input hold from rising CLK

-

0%

Tishivecs

VINITHI input setup to rising CLK

95%

-

Tihhivecs

VINITHI input hold from rising CLK

-

0%

Tisinitram

INITRAM input setup to rising CLK

95%

-

Tihinitram

INITRAM input hold from rising CLK

-

0%

Tovso

Rising CLK to SO valid

-

30%

Tohso

SO hold time from rising CLK

>0%

-

Tissi

SI input setup to rising CLK

95%

-

Tihsi

SI input hold from rising CLK

-

0%

Tisscanen

SCANEN input setup to rising CLK

95%

-

Tihscanen

SCANEN input hold from rising CLK

-

0%

Tistesten

TESTEN input setup to rising CLK

95%

-

Tihtesten

TESTENinput hold from rising CLK

-

0%

Tisserialen

SERIALEN input setup to rising CLK

95%

-

Tihserialen

SERIALEN input hold from rising CLK

-

0%

Tovetminst

Rising CLK to ETM instruction interface valid

-

30%

Tohetminst

ETM instruction interface hold time from rising CLK

>0%

-

Tovetmictl

Rising CLK to ETM instruction control valid

-

30%

Tohetmictl

ETM instruction control hold time from rising CLK

>0%

-

Tovetmstat

Rising CLK to ETMINSTREXEC valid

-

30%

Tohetmstat

ETMINSTREXEC hold time from rising CLK

>0%

-

Tovetmdata

Rising CLK to ETM data interface valid

-

30%

Tohetmdata

ETM data interface hold time from rising CLK

>0%

-

Tovetmnwait

Rising CLK to ETMnWAIT valid

-

30%

Tohetmnwait

ETMnWAIT hold time from rising CLK

>0%

-

Tovetmdctl

Rising CLK to ETM data control valid

-

30%

Tohetmdctl

ETM data control hold time from rising CLK

>0%

-

Tovetmcfg

Rising CLK to ETM configuration valid

-

30%

Tohetmcfg

ETM configuration hold time from rising CLK

>0%

-

Tovetmcpif

Rising CLK to ETM coprocessor signals valid

-

30%

Tohetmcpif

ETM coprocessor signals hold time from rising CLK

>0%

-

Tovetmdbg

Rising CLK to ETM debug signals valid

-

30%

Tohetmdbg

ETM debug signals hold time from rising CLK

>0%

-

Tisetmen

ETMEN input setup to rising CLK

50%

-

Tihetmen

ETMEN input hold from rising CLK

-

0%

Note

The VINITHI pin is specified as 95% of the cycle because it is for input configuration during reset and can be considered static.

The INTEST wrapper inputs/outputs are specified as 95% of the cycle as they are production test related and expected to operate at typically 50% of the functional clock rate.

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