2.3. CP15 register map summary

The ARM946E-S incorporates CP15 for system control. CP15 allows configuration of the caches, tightly-coupled SRAM, and protection unit. It also allows configuration of ARM946E-S system options including big or little-endian operation. The register map for CP15 is shown in Table 2.1.

Table 2.1. CP15 register map

Register

Read

Write

0

ID code [1]

Unpredictable

0

Cache type a

Unpredictable

0

Tightly-coupled memory size a

Unpredictable

1

Control

Control

2

Cache configuration [2]

Cache configuration b

3

Write buffer control

Write buffer control

4

Unpredictable

Unpredictable

5

Access permission b

Access permission b

6

Protection region base and size a

Protection region base and size a

7

Unpredictable

Cache operations

8

Unpredictable

Unpredictable

9

Cache lockdown b

Cache lockdown b

9

Tightly-coupled memory region b

Tightly-coupled memory region b

10

Unpredictable

Unpredictable

11

Unpredictable

Unpredictable

12

Unpredictable

Unpredictable

13

Process ID

Process ID

14

Unpredictable

Unpredictable

15

RAM and TAG BIST test a

RAM and TAG BIST test a

15

Test state a

Test state a

15

Cache debug index a

Cache debug index a

[1] Register location provides access to more than one register. The register accessed depends on the value of the opcode_2 or CRm field. See the register description for details.

[2] Separate registers for instruction and data. See the register description for details.

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