2.3.5. Register 1, Control register

This register contains the control bits of the ARM946E-S. All reserved bits must either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and write this register:

MRC p15, 0, rd, c1, c0, 0; read control register
MCR p15, 0, rd, c1, c0, 0; write control register

Table 2.9 lists the functions controlled by register 1.

Table 2.9. Register 1, control register

Register bit

Function

31:20

Reserved (SBZ)

19

Instruction RAM load mode

18

Instruction RAM enable

17

Data RAM load mode

16

Data RAM enable

15

Configure disable loading TBIT

14

Round-robin replacement

13

Alternate vector select

12

ICache enable

11:8

Reserved (SBZ)

7

Big-endian

6:3

Reserved (SBO)

2

DCache enable

1

Reserved (SBZ)

0

Protection unit enable

The bits in the control register have the following function.

Bit 19, Instruction RAM load mode

This bit controls the operation of the instruction RAM load mode.

You can use the instruction RAM load mode for initializing the instruction RAM. The instruction RAM load mode allows you to load data into ARM registers from either data cache or main memory, and then write to the same address but within the tightly-coupled instruction RAM. This allows you to copy boot code from memory located at address 0x0 into the instruction RAM which, when enabled, also exists at address 0x0. The operation of the load mode is described in I-SRAM load mode.

At reset this bit is cleared.

Bit 18, Instruction RAM enable

This bit controls operation of the tightly-coupled instruction RAM. When the instruction RAM is enabled, all instruction and data accesses to the instruction RAM address range access the instruction RAM.

At reset this bit is cleared.

Bit 17, Data RAM load mode

This bit controls the operation of the data RAM load mode.

You can use the data RAM load mode for initializing the data RAM. The data RAM load mode allows you to load data into ARM registers from either data cache or main memory, and then write to the same address but within the tightly-coupled data RAM. The operation of the load mode is described in I-SRAM load mode.

At reset this bit is cleared.

Bit 16, Data RAM enable

This bit controls operation of the tightly-coupled data RAM. When the data RAM is enabled, it takes precedence over the data cache and AHB for data accesses.

At reset this bit is cleared.

Bit 15, Configure disable loading TBIT

This bit controls the behavior of load PC instructions. When LOW the ARMv5TExP-specific behavior is enabled, and bit 0 of the loaded data is used to control the entry into Thumb state when the PC (r15) is the destination register. When HIGH, this ARMv5TExP behavior is disabled.

At reset this bit is cleared.

Bit 14, Round-robin replacement

This bit controls the cache replacement algorithm.

When HIGH, round-robin replacement is used. When LOW, a pseudo-random replacement algorithm is used.

At reset this bit is cleared.

Bit 13, Alternate vectors select

This bit controls the base address used for the exception vectors.

When LOW, the base address for the exception vectors is 0x00000000. When HIGH, the base address is 0xFFFF0000.

Note

This bit is initialized either HIGH or LOW during system reset, depending on the value of the input pin, VINITHI. This allows you to define the exception vector location during reset to suit the boot mechanism of the application. You can then reprogram this bit as required following system reset.

Bit 12, ICache enable

Controls the behavior of the ICache.

To use the instruction cache, both the protection unit enable bit (bit 0) and the ICache enable bit must be HIGH. This can be done with a single write to register 1.

At reset this bit is cleared.

Bit 7, Endian

Selects the endian configuration of the ARM946E-S. When this bit is HIGH, big-endian configuration is selected. When LOW, little-endian configuration is selected.

At reset this bit is cleared.

Bit 2, DCache enable

This bit controls the behavior of the DCache.

To use the data cache, both the protection unit enable bit (bit 0) and the DCache enable bit must be HIGH. This can be done with a single write to register 1.

At reset this bit is cleared.

Bit 0, Protection unit enable

This bit controls the operation of the ARM946E-S protection unit.

At reset this bit is cleared. This disables the protection unit, and as a result disables the instruction and data caches and the write buffer.

At least one protection region (see Register 6, Protection region/base size registers and Chapter 4 Protection Unit) must be programmed before the protection unit is enabled.

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