6.4. AHB clocking

The ARM946E-S design uses a single rising-edge clock CLK to time all internal activity. In many systems in which the ARM946E-S is embedded, you might prefer to run the AHB at a lower rate. To support this requirement, the ARM946E-S requires a clock enable, HCLKEN, to time AHB transfers.

The HCLKEN input is driven HIGH around a rising edge of the ARM946E-S CLK to indicate that this rising-edge is also a rising-edge of HCLK. HCLK must be synchronous to the ARM946E-S CLK.

When the ARM9E-S is running from tightly-coupled SRAM or performing writes using the write buffer, the ARM946E-S HCLKEN and HREADY inputs are not used to generate the SYSCLKEN core stall signal. The core is only stalled by SRAM stall cycles or if the write buffer overflows. This means that the ARM9E-S is executing instructions at the faster CLK rate and is effectively decoupled from the HCLK domain AHB system.

If, however, you want to perform an AHB read access or unbuffered write, the core is stalled until the AHB transfer has completed. As the AHB system is being clocked by the lower rate HCLK, HCLKEN is examined to detect when to drive out the AHB address and control to start an AHB transfer. HCLKEN is then required to detect the following rising edges of HCLK so that the BIU knows the access has completed.

If the slave being accessed at the HCLK rate has a multi-cycle response, the HREADY input to the ARM946E-S is driven LOW until the data is ready to be returned. The BIU must therefore perform a logical AND on the HREADY response with HCLKEN to detect that the AHB transfer has completed. When this is the case, the ARM9E-S core is enabled by reasserting SYSCLKEN.

Note

When an AHB access is required, the core is stalled until the next HCLKEN pulse is received, before it can start the access, and then until the access has completed. This stall before the start of the access is a synchronization penalty and the worst case can be expressed in CLK cycles as the HCLK to CLK ratio minus 1.

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