5.1. ARM946E-S SRAM requirements

The ARM946E-S tightly-coupled SRAM is built from blocks of ASIC library compiled SRAM. The instruction SRAM (I-SRAM) and data SRAM (D-SRAM) can each be of any size supported by the protection unit, from 0 bytes to 1MB, although to ease implementation the size must be an integer power of two. The (I-SRAM) and (D-SRAM) can have different sizes.

ARM946E-S supports synchronous SRAM for the tightly-coupled RAM. The memory cells must be capable of returning data to the ARM9E-S core in a single cycle. This requirement applies to both the I-SRAM and D-SRAM.

To allow the I-SRAM to be initialized, and for access to literal tables during execution, the data interface of the ARM9E-S core must be able to access the I-SRAM. This means that the ARM946E-S must multiplex the instruction and data addresses before entering the I-SRAM. It also means that the instruction data is routed to both the instruction and data interfaces of the core. See Figure 1.1 for details of this data and address multiplexing.

Figure 5.1 shows a typical read cycle (I-SRAM shown).

Figure 5.1. SRAM read cycle

The I-SRAM is located at address 0x00000000 in the memory map. This simplifies the implementation of the design by removing the need for complex address comparators on both the instruction and data interfaces of the ARM9E-S core to generate the chip select logic for the SRAM. Fixing the SRAM location at 0x0 allows an address decode to control the chip selects to give greater power efficiency.

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