7.1. About the coprocessor interface

ARM946E-S fully supports the connection of on-chip coprocessors through an external coprocessor interface. All types of coprocessor instructions are supported. For a description of all the interface signals referred to in this chapter, see the ARM9E-S Technical Reference Manual.

Coprocessors determine the instructions they must execute using a pipeline follower in the coprocessor. As each instruction arrives from memory it enters both the ARM pipeline and the coprocessor pipeline. To avoid a critical path for the instruction being registered by the coprocessor, the coprocessor pipeline operates one clock cycle behind the ARM9E-S core pipeline. However, there is a mechanism inside ARM946E-S that stalls the ARM9E-S pipeline so the external coprocessor pipeline can catch up with the processor pipeline. So, practically, consider that the two pipelines are synchronized. The ARM9E-S core informs the coprocessor when instructions move from Decode into Execute, and whether the instruction has to be executed.

To enable coprocessors to continue executing coprocessor data operations while the ARM9E-S core pipeline is stalled (for example, when waiting for a cache linefill to occur), the coprocessor receives the clock CLK, and a clock enable signal CPCLKEN.

If CPCLKEN is LOW on the rising edge of CPCLK then the ARM9E-S core pipeline is stalled and the coprocessor pipeline must not advance. Figure 7.1 indicates the timing for these signals and when the coprocessor pipeline must advance its state.

Figure 7.1. Coprocessor clocking

Coproc clock shows the result of ORing CLK with the inverse of CPCLKEN. This is one technique for generating a clock that reflects the ARM9E-S core pipeline advancing.

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