7.2. LDC/STC

The LDC and STC instructions are used respectively to transfer data to and from external coprocessor registers and memory. For the ARM946E-S, the memory can be either internal memory (cache or tightly-coupled memory) or AHB depending on the address range of the access and the protection unit settings.

The cycle timing for these operations is shown in Figure 7.2.

Figure 7.2. LDC/STC cycle timing

In this example, four words of data are transferred. The number of words transferred is determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.

As with all other instructions, the ARM9E-S performs the main Decode off the rising edge of the clock during the Decode stage. From this, the core commits to executing the instruction and so performs an instruction Fetch. The coprocessor instruction pipeline keeps in step with ARM9E-S core by monitoring nCPMREQ. This is a registered version of the ARM9E-S core instruction memory request signal InMREQ.

At the rising edge of CLK, if CPCLKEN is HIGH, and nCPMREQ is LOW, an instruction Fetch is taking place, and CPINSTR[31:0] contains the fetched instruction on the next rising edge of the clock, when CPCLKEN is HIGH.

This means that:

  1. The last instruction fetched enters the Decode stage of the coprocessor pipeline.

  2. The instruction in the Decode stage of the coprocessor pipeline enters its Execute stage.

  3. The fetched instruction is sampled.

In all other cases, the ARM9E-S pipeline is stalled, and the coprocessor pipeline does not advance.

During the Execute stage, the condition codes are compared with the flags to determine whether the instruction really executes or not. The output CPPASS is asserted (HIGH) if the instruction in the Execute stage of the coprocessor pipeline:

If a coprocessor instruction busy-waits, CPPASS is asserted on every cycle until the coprocessor instruction is executed. If an interrupt occurs during busy-waiting, CPPASS is driven LOW, and the coprocessor stops execution of the coprocessor instruction.

Another output, CPLATECANCEL, cancels a coprocessor instruction when the instruction preceding it causes a Data Abort. This is valid on the rising edge of CLK on the cycle that follows the first Execute cycle of the coprocessor instruction. This is the only cycle that CPLATECANCEL can be asserted in.

On the rising edge of the clock, the ARM9E-S processor examines the coprocessor handshake signals CHSDE[1:0] or CHSEX[1:0]:

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