7.3. MCR/MRC

MCR/MRC cycles look very similar to STC/LDC. An example, with a busy-wait state, is shown in Figure 7.3.

Figure 7.3. MCR/MRC transfer timing with busy-wait

First nCPMREQ is driven LOW to denote that the instruction on CPINSTR[31:0] is entering the Decode stage of the pipeline. This causes the coprocessor to decode the new instruction and drive CHSDE[1:0] as required. In the next cycle nCPMREQ is driven LOW to denote that the instruction has now been issued to the Execute stage. If the condition codes pass, and therefore, the instruction is to be executed, then the CPPASS signal is driven HIGH and the CHSDE[1:0] handshake bus is examined. It is ignored in all other cases.

For any successive Execute cycles the CHSEX[1:0] handshake bus is examined. When the LAST condition is observed, the instruction is committed. In the case of an MCR, the CPDOUT[31:0] bus is driven with the registered data during the coprocessor Write stage. In the case of an MRC, CPDIN[31:0] is sampled at the end of the ARM9E-S core Memory stage and written to the destination register during the next cycle.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
Non-Confidential