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Home > Coprocessor Interface > Interlocked MCR |
If the data for an MCR
operation is not
available inside the ARM9E-S core pipeline during its first Decode
cycle, then the ARM9E-S core pipeline interlocks for one or more cycles
until the data is available. An example of this is where the register
being transferred is the destination from a preceding LDR
instruction.
In this situation the MCR
instruction enters
the Decode stage of the coprocessor pipeline, and then remains there
for a number of cycles before entering the Execute stage.
Figure 7.4 gives
an example of an interlocked MCR
that also has
a busy-wait state.