CDP instructions normally execute in a single cycle. Like all the previous cycles, nCPMREQ is driven LOW to signal when an instruction is entering the Decode and then the Execute stage of the pipeline. If the instruction really is to be executed, the CPPASS signal is driven HIGH during the Execute cycle. If the coprocessor can execute the instruction immediately it drives CHSDE[1:0] with LAST. If the instruction requires a busy-wait cycle, the coprocessor drives CHSDE[1:0] with WAIT and then CHSEX[1:0] with LAST.

Figure 7.5 shows a CDP cancelled because the previous instruction caused a Data Abort.

The CDP instruction enters the Execute stage of the pipeline and is signaled to execute by CPASS. In the following cycle CPLATECANCEL is asserted. This causes the coprocessor to terminate execution of the CDP instruction and for it to cause no state changes to the coprocessor.