7.7. Busy-waiting and interrupts

The coprocessor is permitted to stall, or busy-wait, the processor during the execution of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor instruction. To do so, the coprocessor associated with the Decode stage instruction drives WAIT onto CHSDE[1:0]. When the instruction concerned enters the Execute stage of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles as necessary to keep the instruction in the busy-wait loop.

For interrupt latency reasons the coprocessor can be interrupted while busy-waiting. This causes the instruction to be abandoned. Abandoning execution is done through CPPASS. The coprocessor must monitor the state of CPPASS during every busy-wait cycle. If it is HIGH, the instruction must still be executed. If it is LOW, the instruction must be abandoned.

Figure 7.7 shows a busy-waited coprocessor instruction abandoned due to an interrupt. CPLATECANCEL is also asserted as a result of the Execute interruption.

Figure 7.7. Busy-waiting and interrupts

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
Non-Confidential