8.2.3. ARM946E‑S debug target

The ARM9E‑S core within the ARM946E-S has hardware extensions that ease debugging at the lowest level. The debug extensions:

The following major blocks of the ARM9E‑S are shown in the Figure 8.3:

ARM9E-S CPU Core

With hardware support for debug.

EmbeddedICE-RT logic

This is a set of registers and comparators used to generate debug exceptions (such as breakpoints). This unit is described in Overview of EmbeddedICE-RT.

TAP controller

This controls the action of the scan chains using a JTAG serial interface.

Figure 8.3. ARM9E‑S block diagram

The ARM9E-S debug model is extended within the ARM946E-S by the addition of scan chain 15. This is used for debug access to the CP15 register bank, to allow you to configure the system state within the ARM946E-S while in debug state, for instance to enable or disable the SRAM before performing a debug load or store.

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