8.9. Overview of EmbeddedICE-RT

The ARM9E‑S EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM9E‑S core within the ARM946E-S.

EmbeddedICE-RT is programmed serially using the ARM9E‑S TAP controller. Figure 8.10 illustrates the relationship between the core, EmbeddedICE-RT, and the TAP controller, showing only the signals that are pertinent to EmbeddedICE-RT.

Figure 8.10. The ARM9E‑S, TAP controller, and EmbeddedICE-RT

The EmbeddedICE-RT logic comprises:

The debug control register and the debug status register provide overall control of EmbeddedICE-RT operation.

You can program one or both watchpoint units to halt the execution of instructions by the core. Execution halts when the values programmed into EmbeddedICE-RT match the values currently appearing on the address bus, data bus, and various control signals.


You can mask bits so that their values do not affect the comparison.

You can configure each watchpoint unit to be either a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be data-dependent in halt mode debug.

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