8.11.3. Debug status register

A debug monitor can use the coprocessor 14 debug status register when the ARM9E-S is configured into real-time debug mode.

The coprocessor 14 debug status register is a 1-bit wide read/write register with the format shown in Figure 8.12.

Figure 8.12. Coprocessor 14 debug status register format

Bit 0 of the register, the DbgAbt bit, indicates whether the processor took a Prefetch or Data Abort in the past because of a breakpoint or watchpoint. If the ARM9E-S core takes a Prefetch Abort as a result of a breakpoint or watchpoint, then the bit is set. If on a particular instruction or data fetch, both the debug abort and external abort signals are asserted, the external abort takes priority and the DbgAbt bit is not set. You can read/write the DbgAbt bit using MRC/MCR instructions.

A typical use of this bit is by a real-time debug aware abort handler. This examines the DbgAbt bit to determine whether the abort has been externally or internally generated. If the DbgAbt bit is set, the abort handler initiates communication with the debugger over the comms channel.

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