8.12. Real-time debug

The ARM9E-S within ARM946E-S contains logic that allows you to debug a system without stopping the core entirely. This allows the continued servicing of critical interrupt routines while the core is being interrogated by the debugger. Setting bit 4 of the debug control register enables the real-time debug features of ARM9E-S. When this bit is set, the EmbeddedICE-RT logic is configured so that a breakpoint/watchpoint causes the ARM to enter abort mode, taking the Prefetch Abort or Data Abort vectors respectively. You must be aware of a number of restrictions when the ARM is configured for real-time debugging:

When an abort is generated by the monitor mode, it is recorded in the debug status register in coprocessor 14 (see Debug status register).

Because the monitor mode debug does not put the ARM9E-S into debug state, you must now change the contents of the watchpoint registers while external memory accesses are taking place, rather than being changed when in debug state. If the watchpoint registers are written to during an access, all matches from the affected watchpoint unit using the register being updated are disabled for the cycle of the update.

If false matches can occur during changes to the watchpoint registers, caused by old data in some registers and new data in others, then you must:

  1. Disable that watchpoint unit using the control register for that watchpoint unit.

  2. Change the other registers.

  3. Re-enable the watchpoint unit by rewriting the control register.

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