10.3. BIST of memory arrays

Adding a simple memory test controller allows you to perform an exhaustive test of the memory arrays. You can activate the BIST test using an MCR to the CP15 BIST control register.

When you perform a BIST test on an SRAM, the functional enable for that SRAM is automatically disabled, forcing all memory accesses to that SRAM address space to go to the AHB. This enables you to run BIST tests in the background, for instance the instruction SRAM can be BIST tested, while code is executed over the AHB.

Serial scan access to the CP15 BIST operations is also provided for production test purposes, using a special mode of operation of the INTEST wrapper. See ARM946E-S INTEST wrapper.

You can also perform limited BIST testing in debug state by using scan chain 15 to access the CP15 BIST control register. This is not necessarily recommended as the BIST test corrupts the contents of the SRAM being tested.

You can achieve full programmer control over the BIST mechanism through five registers that are mapped to CP15 register 15 address space. For details of the MCR/MRC instructions used to access these registers, see Register 15, RAM and TAG BIST test registers.

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