B.2. Clock interface signals

Table B.1 describes the ARM946E-S clock interface signals.

Table B.1. Clock interface signals

Name

Direction

Description

CLK

System clock

Input

This clock times all operations in the ARM946E-S design. All outputs change from the rising edge and all inputs are sampled on the rising edge. The clock can be stretched in either phase.

Using the HCLKEN signal, this clock also times AHB operations.

Using the DBGTCKEN signal, this clock also times debug operations.

HCLKEN

Input

Synchronous enable for AHB transfers. When HIGH indicates that the next rising edge of CLK is also a rising edge of HCLK in the AHB system that the ARM946E-S is embedded in. Must be tied HIGH in systems where CLK and HCLK are intended to be the same frequency.

DBGTCKEN

Input

Synchronous enable for debug logic accessed using the JTAG interface. When HIGH on the rising edge of CLK the debug logic can advance.

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