B.3. AHB signals

Table B.2 describes the ARM946E-S AHB signals.

Table B.2. AHB signals

Name

Direction

Description

HADDR[31:0]

Address bus

Output

The 32-bit AHB system address bus.

HBURST[2:0]

Burst type

Output

Indicates if the transfer forms part of a burst. The ARM946E-S supports SINGLE transfer (000) and INCRemental burst of unspecified length (001).

HBUSREQ

Bus request

Output

Indicates that the ARM946E-S requires the bus.

HGRANT

Bus grant

Input

Indicates that the ARM946E-S is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADY is HIGH, so the ARM946E-S gets access to the bus when both HREADY and HGRANT are HIGH.

HLOCK

Request locked transfers

Output

When HIGH, indicates that the ARM946E-S requires locked access to the bus and no other master must be granted until this signal has gone LOW. Asserted by the ARM946E-S when executing SWP instructions to AHB address space.

HPROT[3:0]

Protection control

Output

Indicates that the ARM946E-S transfer is an opcode fetch (0--0) or data access (0--1). Indicates if the transfer is User mode access (0-0-) or a Supervisor mode access (0-1-). Indicates that an access is nonbufferable (00--) or bufferable (01--). Bit [3] is tied LOW indicating noncachable.

HRDATA[31:0]

Read data bus

Input

The 32-bit read data bus transfers data from a selected bus slave to the ARM946E-S during read operations.

HREADY

Transfer done

Input

When HIGH indicates that a transfer has finished on the bus. This signal can be driven LOW by the selected bus slave to extend a transfer.

HRESETn

Not reset

Input

Asynchronously asserted LOW input used to initialize the ARM946E-S system state. Synchronously de-asserted.

HRESP[1:0]

Transfer response

Input

The transfer response from the selected slave provides additional information on the status of the transfer. The response can be OKAY (00), ERROR (01), RETRY (10), or SPLIT (11).

HSIZE[2:0]

Transfer size

Output

Indicates the size of an ARM946E-S transfer. This can be Byte (000), Halfword (001), or Word (010). Bit [2] is tied LOW.

HTRANS[1:0]

Transfer type

Output

Indicates the type of ARM946E-S transfer. This can be IDLE (00), NONSEQ (10), or SEQ (11).

HWDATA[31:0]

Write data bus

Output

The 32-bit write data bus transfers data from the ARM946E-S to a selected bus slave during write operations.

HWRITE

Transfer direction

Output

When HIGH indicates a write transfer. When LOW indicates a read transfer.

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