B.7. Miscellaneous signals

Table B.6 describes the ARM946E-S miscellaneous signals.

Table B.6. Miscellaneous signals

Name

Direction

Description

BIGENDOUT

Output

When HIGH, the ARM946E-S treats bytes in memory as being in big-endian format. When LOW, memory is treated as little-endian.

nFIQ

Not fast interrupt request

Input

This is the Fast Interrupt Request signal. This signal must be synchronous to CLK.

nIRQ

Not interrupt request

Input

This is the Interrupt Request signal. This signal must be synchronous to CLK.

VINITHI

Exception vector location at reset

Input

Determines the reset location of the exception vectors. When LOW, the vectors are located at 0x00000000. When HIGH, the vectors are located at 0xFFFF0000.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
Non-Confidential