10.3.3. Pause modes

ARM recommends that you use the following production test sequence for the SRAM:

  1. Test each SRAM using a full test.

  2. Test the BIST hardware for each SRAM.

To allow testing of the BIST hardware, a pause mechanism enables you to halt the BIST test. This allows you to corrupt data within the SRAM. The sequence for this is:

  1. Write the address for the location to be corrupted with an MCR to the relevant BIST address register

  2. Write the corrupted data using a MCR to the BIST general register.

You can then restart the test using an MCR to the BIST control register and check to see that the corrupted data causes the test to fail. You can read the fail address and data from the BIST address and general registers.

In addition to controlling the addressing within the address and general registers, the pause bit also controls the progression of the BIST algorithm as described in:


ARM recommends that you do not write application code that relies on the presence of the BIST pause mode. ARM does not guarantee to support this feature in future versions of the ARM946E-S.

Auto pause

If you set the pause bit in the BIST control register before you activate the test, the test runs in auto pause mode. The BIST test pauses at predetermined points of the BIST algorithm, for instance when the algorithm has reached the top or the bottom of the memory array being tested.

You can poll the BIST control register to detect when a test has paused (the running flag is LOW). You can then corrupt the data, as described in Pause modes, before you restart the BIST test.

User pause

If the pause bit is clear when the test is activated, the test is run in user pause mode. The BIST algorithm is only paused by an MCR to the BIST control register setting the pause bit for the SRAM being tested. The SRAM contents are then corrupted as previously. This stops the BIST algorithm at a potentially unknown point, resulting in the possibility that the corrupted data is overwritten by the BIST algorithm and therefore not cause a test to fail.


The user pause mode is provided for production test debugging where you might wish to shorten a test by pausing the algorithm very early. The auto-pause mechanism is recommended to provide deterministic BIST hardware testing for all other occasions.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A