8.3. The JTAG state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure 8.4 shows the state transitions that occur in the TAP controller.

The state numbers are also shown on the diagram. These are output from the ARM946E-S on the TAPSM[3:0] bits.

Figure 8.4. Test access port (TAP) controller state transitions[1]



[1] From IEEE Std 1149.1-1990. Copyright 1999IEEE. All rights reserved.

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