2.3.3. Register 0, Cache type register

This is a read-only register that contains information about the size and architecture of the instruction cache (ICache) and data cache (DCache), allowing operating systems to establish how to perform operations such as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.

The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1. For example:

MRC p15,0,Rd,c0,c0,1; returns cache details

The format of the register is shown in Table 2.4.

Table 2.4. Cache type register format

Register bits

Function

Value

31:29

Reserved

000

28:25

Cache type

0111

24

Harvard/Unified

1 (defines Harvard cache)

23:22

Reserved

00

21:18

DCache size

Implementation-specific

17:15

DCache associativity

Implementation-specific

14

DCache base size

Implementation-specific

13:12

DCache words per line

10 (defines 8 words per line)

11:10

Reserved

00

9:6

ICache size

Implementation-specific

5:3

ICache associativity

Implementation-specific

2

ICache base size

Implementation-specific

1:0

ICache words per line

10 (defines 8 words per line)

Bits [28:25] indicate which major cache class the implementation falls into. 0x7 means that the cache provides:

Bits [21:18] give the data cache size. Bits [9:6] give the instruction cache size. Table 2.5 lists the meaning of values used for cache size encoding.

Table 2.5. Cache size encoding

Bits [21:18] and

bits[9:6]

Cache size

b0000

0KB

b0011

4KB

b0100

8KB

b0101

16KB

b0110

32KB

b0111

64KB

b1000

128KB

b1001

256KB

b1010

512KB

b1011

1MB

Bits [17:15] give the data cache associativity. Bits [5:3] give the instruction cache associativity. Table 2.6 lists the meaning of values used for cache associativity encoding.

Table 2.6. Cache associativity encoding

Bits [17:15] and

bits [5:3]

Associativity

000

Direct mapped

010

4

The cache associativity fields in the cache type register are implementation-specific (implementor-defined). Therefore, if the implementation has an instruction or data cache, the associativity for that cache is set to 010 to indicate a four-way set associative cache. If either cache is not included in a specific implementation, then the associativity field for that cache is set to 000 to indicate that the cache is absent.

The cache base size and cache size fields are generated within the cache blocks to avoid having to resynthesize the design for different cache sizes.

Bit 14 gives the data cache base size.

Bit 2 gives the instruction cache base size.

The base size bits are implementation-specific. If the implementation has an instruction or data cache, the base size bit for that cache is set to 0, indicating that the cache type parameters are valid. If either cache is not included for a specific implementation, the relevant base size is set to 1, indicating that the cache is absent.

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