8.4.4. Scan chain 15

Scan chain 15 allows debug access to the CP15 register bank and allows the cache to be interrogated. Scan chain 15 is 39 bits long.

The order of scan chain 15 from the DBGTDI input to the DBGTDO output is shown in Table 8.4.

Table 8.4. Scan chain 15 addressing mode bit order

Bits

Contents

38

Read = 0, write = 1

37:32

CP15 register address

31:0

CP15 data value

The mapping of the CP15 register address field of scan chain 15 to CP15 registers is shown in Table 8.5.

Table 8.5. Mapping of scan chain 15 address field to CP15 registers

Address

Register

[37]

[36:33]

[32]

Number

Name

Type

0

0000

0

C0.ID

ID register

Read

0

0000

1

C0.C

Cache type

Read

0

0001

0

C1

Control

Read/write

0

0010

0

C2.D

Data cachable bits

Read/write

0

0010

1

C2.I

Instruction cachable bits

Read/write

0

0011

0

C3

Write buffer control

Read/write

0

0100

0

C0.M

Tightly-coupled memory size

Read

0

0101

0

C5.D

Data space access permissions

Read/write

0

0101

1

C5.I

Instruction address access permissions

Read/write

1

<Crm>[1]

0

C6.[7:0]

Memory region protection

Read/write

0

0111

0

C7.FD

Flush data cache

Write

0

0111

1

C7.FI

Flush instruction cache

Write

0

1110

0

C7.FD.s

Flush DCache single (uses C15.C.Ind)

Write

0

1110

1

C7.FI.s

Flush ICache single (uses C15.C.Ind)

Write

1

1010

1

C7.CD.s

Clean DCache single (uses C15.C.Ind)

Write

0

1001

0

C9.D

Data cache lock-down

Read/write

0

1001

1

C9.I

Instruction cache lock-down

Read/write

1

1000

1

C9.Dram

Data SRAM size/location

Read/write

1

1001

1

C9.Iram

Instruction SRAM size/location

Read/write

0

1101

1

C13.TPID

Trace process identifier

Read/write

0

1111

0

C15.State

Test state

Read/write

0

1111

1

C15.TAG

TAG BIST control

Read/write

1

1111

1

C15.RAM

Cache RAM BIST control

Read/write

1

1101

0

C15.C.Ind

Cache index (address/segment)

Read/write

0

1010

0

C15.DC

Data cache read/write (uses C15.C.Ind)

Read/write

0

1010

1

C15.IC

Instruction cache read/write (uses C15.C.Ind)

Read/write

0

1011

0

C15.DT

Data tag read/write (uses C15.C.Ind)

Read/write

0

1011

1

C15.IT

Instruction tag read/write (uses C15.C.Ind)

Read/write

1

1110

1

C15.Mem

Memory RAM BIST control

Read/write

[1] For CP15 register 6, CRm corresponds to the region number (0 to 7).

In the SHIFT-DR state of the TAP state machine, the read/write bit, the register address and the register value for writing, are shifted in.

For a write, the register value is updated when the UPDATE-DR state is reached.

For reading, return to SHIFT-DR through CAPTURE-DR to shift out the register value.

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