B.5. Debug signals

Table B.4 describes the ARM946E-S debug signals.

Table B.4. Debug signals

Name

Direction

Description

COMMRX

Communications channel receive

Output

When HIGH denotes that the comms channel receive buffer contains valid data waiting to be read.

COMMTX

Communications channel transmit

Output

When HIGH, denotes that the comms channel transmit buffer is empty.

DBGACK

Debug acknowledge

Output

When HIGH indicates that the processor is in debug state.

DBGDEWPT

Data watchpoint

Input

Asserted by external hardware to halt execution of the processor for debug purposes. If HIGH at the end of a data memory request cycle, it causes the ARM946E-S to enter debug state.

DBGEN

Debug enable

Input

Enables the debug features of the processor. This signal must be tied LOW if debug is not required.

DBGEXT[1:0]

EmbeddedICE-RT external input

Input

Input to the EmbeddedICE-RT logic allows breakpoints/watchpoints to be dependent on external conditions.

DBGIEBKPT

Instruction breakpoint

Input

Asserted by external hardware to halt execution of the processor for debug purposes. If HIGH at the end of an instruction fetch, it causes the ARM946E-S to enter debug state if that instruction reaches the Execute stage of the processor pipeline.

DBGINSTREXEC

Instruction executed

Output

Indicates that the instruction in the Execute stage of the processor’s pipeline has been executed.

DBGRNG[1:0]

EmbeddedICE-RT Rangeout

Output

Indicates that the corresponding EmbeddedICE-RT watchpoint register has matched the conditions currently present on the address, data, and control buses. This signal is independent of the state of the watchpoint enable control bit.

DBGRQI

Internal debug request

Output

Represents the debug request signal that is presented to the core debug logic. This is a combination of EDBGRQ and bit 1 of the debug control register.

EDBGRQ

External debug request

Input

An external debugger can force the processor into debug state by asserting this signal.

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