You must initialize the I-SRAM with the required code image before execution from the I-SRAM.

You can initialize the I-SRAM by writing to the memory from the AM9E-S core data interface.

The I-SRAM load mode allows this to be done in an efficient manner. Using the load mode allows you to copy from an address in the data cache or external memory into the same address within the I-SRAM.

The I-SRAM load mode bit of CP15 Register 1 inhibits reads from the I-SRAM, forcing reads from addresses that are within the I-SRAM address range to access either main memory, the data cache. Writes to addresses that are within the I-SRAM range are not affected by the Instruction Load Mode bit.

The procedure for initializing the I-SRAM using the load mode is as follows:

A suggested assembler code sequence for this procedure is:

	MOV R0, #0 						; Initialize pointer

	LDR R1, =ImageTop 						; Define end of code image

	MRC p15, 0, R2, c1, c0, 0 						; Read Control Register

	ORR R2, R2, #&C0000

	MCR p15, 0, R2, c1, c0, 0 						; Enable Instruction RAM and Load Mode

CopyLoop

	LDMIA R0, {R2 - R9} 						; Load 8 registers from main memory

	STMIA R0!, {R2 - R9}						; Store 8 regs into instruction SRAM

	CMP R1, R0 						; Check if limit reached

	BGT CopyLoop 						; Repeat if more to do

SWP and SWPB operations to the instruction tightly-coupled memory while it is in load mode have unpredictable results. The read accesses external memory or the data cache, and the write updates the instruction tightly-coupled memory.

SWP and SWPB operations must not be performed to addresses in the instruction tightly-coupled SRAM space while it is in load mode.