5.2.6. D-SRAM load mode

You must initialize the D-SRAM with the required data image before use.

You can initialize the D-SRAM by writing to the memory from the AM9E-S core data interface.

The D-SRAM load mode allows this to be done in an efficient manner. Using the load mode allows you to copy from an address in the data cache or external memory into the same address within the D-SRAM.

The D-SRAM load mode bit of CP15 Register 1 inhibits reads from the D-SRAM, forcing reads from addresses that are within the D-SRAM address range to access either main memory or the data cache. Writes to addresses that are within the D-SRAM range are not affected by the data load mode bit.

The procedure for initializing the D-SRAM using the load mode is as follows:

  1. Enable the D-SRAM and data load mode

  2. Load ARM registers from main memory or data cache

  3. Store ARM registers into data RAM

  4. Increment address pointers and repeat load/store steps until the data image has been copied.

A suggested assembler code sequence for this procedure is:

	LDR R0, #ImageStart 							; Initialise pointer
	LDR R1, =ImageTop							; Define end of data space
	MRC p15, 0, R2, c1, c0, 0							; Read Control Register
	ORR R2, R2, #&30000
	MCR p15, 0, R2, c1, c0, 0	; Enable Data RAM and Load Mode
CopyLoop
	LDMIA R0, {R2 - R9} 						; Load 8 registers from main memory
	STMIA R0!, {R2 - R9}						; Store 8 regs into instruction SRAM
	CMP R1, R0 						; Check if limit reached
	BGT CopyLoop 						; Repeat if more to do

SWP and SWPB operationsto the data tightly-coupled memory while it is in load mode have unpredictable results. The read accesses external memory or the data cache, and the write updates the data tightly-coupled memory.

SWP and SWPB operations must not be performed to addresses in the instruction tightly-coupled SRAM space while it is in load mode.

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