2.3.10. Register 7, Cache operations register

A write to this register can be used to perform the following operations:

The ARM946E-S uses a subset of the ARM architecture v4 functions (defined in the ARM Architecture Reference Manual). The available operations are summarized in Table 2.19.

Table 2.19. Cache operations

ARM instruction



MCR p15, 0, rd, c7, c5, 0

Flush ICache


MCR p15, 0, rd, c7, c5, 1

Flush ICache single entry


MCR p15, 0, rd, c7, c13, 1

Prefetch ICache line


MCR p15, 0, rd, c7, c6, 0

Flush DCache


MCR p15, 0, rd, c7, c6, 1

Flush DCache single entry


MCR p15, 0, rd, c7, c10, 1

Clean DCache entry


MCR p15, 0, rd, c7, c14, 1

Clean and flush DCache entry


MCR p15, 0, rd, c7, c10, 2

Clean DCache entry


MCR p15, 0, rd, c7, c14, 2

Clean and flush DCache entry


[1] The value transferred in Rd should be zero.

The data format for index/segment operations is shown in Figure 2.2.

Figure 2.2. Index and segment format

The size of the index varies depending on the implemented cache size. Table 2.20 shows how the index size changes for the cache sizes supported by the ARM946E-S.

Table 2.20. Index fields for supported cache sizes

Cache size




















For the ICache prefetch operation, the data format is shown in Figure 2.3.

Figure 2.3. ICache address format

Cache clean and flush operations

Cache clean and flush operations can occur during instruction and data linefetches. In such circumstances the linefetch completes before the clean or flush operation is executed.

Drain write buffer

This operation stalls instruction execution until the write buffer is emptied. This is useful in real-time applications where the processor must be sure that a write to a peripheral has completed before program execution continues. An example is where a peripheral in a bufferable region is the source of an interrupt. When the interrupt has been serviced, the request must be removed before interrupts can be re-enabled. This is ensured if a drain write buffer operation separates the store to the peripheral and the enable interrupt functions.

The drain write buffer operation is invoked by a write to register 7 using the following ARM instruction:

MCR cp15, 0, rd, c7, c10, 4; drain write buffer 

This stalls the processor core until any outstanding accesses in the write buffer are completed, that is, until all data is written to external memory.

Wait for interrupt

This operation allows the ARM946E-S to enter a low-power standby mode. When you invoke the operation, the CLKEN signal to the processor core is negated and the cache and tightly-coupled memories are placed in a low-power state until either an interrupt or a debug request occurs. This function is invoked by a write to register 7. The following ARM instruction causes this to occur:

MCR p15, 0, rd, c7, c0, 4; wait for interrupt

This is the preferred encoding for new software. For compatibility with existing software, ARM946E-S also supports the following ARM instruction that has the same affect:

MCR p15, 0, rd, c15, c8, 2; wait for interrupt

This stalls the processor from the time that this instruction is executed until either nFIQ, nIRQ or EDBGRQ are asserted. Also, if the debugger sets the debug request bit in the EmbeddedICE-RT logic control register then this causes the wait for interrupt condition to terminate.

In the case of nFIQ and nIRQ, the processor core is woken up regardless of whether the interrupts are enabled or disabled (that is, independent of the I and F bits in the processor CPSR). The debug related waking only occurs if DBGEN is HIGH, that is, only when debug is enabled.

If interrupts are enabled, the ARM9E-S core is guaranteed to take the interrupt before executing the instruction after the wait for interrupt. If debug request is used to wake up the system, the processor enters debug state before executing any more instructions.

The write buffer continues to drain until empty while the wait for interrupt operation is executing.

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