8.1. About the debug interface

Debug support is implemented using the ARM9E-S core embedded within the ARM946E-S. The ARM946E‑S debug interface is based on IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture. See this standard for an explanation of the terms used in this chapter and for a description of the TAP controller states.

The ARM9E‑S processor core within the ARM946E-S contains hardware extensions for advanced debugging features. These make it easier to develop application software, operating systems, and the hardware itself.

The debug extensions allow you to force the core to be stopped by:

This is known as debug state. In debug state, the core and ARM946E-S memory system are effectively stopped, and isolated from the rest of the system. This is known as halt mode operation and allows you to examine the internal state of the ARM9E-S core, ARM946E-S system, and external AHB state, while all other system activity continues as normal. When debug has been completed, the ARM9E‑S restores the core and system state, and resumes program execution.

The examination of the internal state of the ARM946E-S uses a JTAG-style interface, that allows you to serially insert instructions into the instruction pipeline. This exports the contents of the ARM9E-S core registers. The exported data is serially shifted out without affecting the rest of the system.

In addition, the ARM9E-S supports a real-time debug mode, where instead of generating a breakpoint or watchpoint, an internal Instruction Abort or Data Abort is generated. This is known as monitor mode operation.

When used in conjunction with a debug monitor program activated by the abort exception entry, you can debug the ARM946E-S while allowing the execution of critical interrupt service routines. The debug monitor program typically communicates with the debug host over the ARM946E-S debug communication channel. Real-time debug is described in Real-time debug.

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