2.3.6. Register 2, Cache configuration registers

These registers contain the cachable attributes for the eight areas of memory. Individual control is provided for the I and D caches. If the opcode_2 field = 0, then the data cache bits are programmed. If the opcode_2 field = 1, then the instruction cache bits are programmed. To read and write these registers:

MRC p15, 0, rd, c2, c0, 0; read data cachable bits
MRC p15, 0, rd, c2, c0, 1; read instruction cachable bits
MCR p15, 0, rd, c2, c0, 0; write data cachable bits
MCR p15, 0, rd, c2, c0, 1; write instruction cachable bits

The format for the cachable bits in data and instruction areas is the same, and is given in Table 2.10.

Table 2.10. Programming instruction/data cachable bits

Register bit

Function

7

Cachable bit (C_7) for area 7

6

Cachable bit (C_6) for area 6

5

Cachable bit (C_5) for area 5

4

Cachable bit (C_4) for area 4

3

Cachable bit (C_3) for area 3

2

Cachable bit (C_2) for area 2

1

Cachable bit (C_1) for area 1

0

Cachable bit (C_0) for area 0

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