2.3.9. Register 6, Protection region/base size registers

These registers define the protection region base address/size registers. You can define eight programmable regions using these registers. The values are ignored when the protection unit is disabled, and on reset only the region enable bit for each region is reset to 0. All other bits are undefined. You must program at least one memory region before you enable the protection unit.

The instructions used to access the eight protection region/base size registers are listed in Table 2.16.

Table 2.16. Accessing protection region/base size registers

ARM instruction

Protection region/

base size register

MCR/MRC p15, 0, rd, c6, c7, 0

Memory region 7

MCR/MRC p15, 0, rd, c6, c6, 0

Memory region 6

MCR/MRC p15, 0, rd, c6, c5, 0

Memory region 5

MCR/MRC p15, 0, rd, c6, c4, 0

Memory region 4

MCR/MRC p15, 0, rd, c6, c3, 0

Memory region 3

MCR/MRC p15, 0, rd, c6, c2, 0

Memory region 2

MCR/MRC p15, 0, rd, c6, c1, 0

Memory region 1

MCR/MRC p15, 0, rd, c6, c0, 0

Memory region 0

Each protection region/base size register has the format shown in Table 2.17.

Table 2.17. Protection region/base size register format

Register bit

Function

31:12

Region base

5:1

Area size

0

1 = Region enable

0 = Region disable

Reset to 0.

You must align the region base to an area size boundary, where the area size is defined in its respective protection region register. The behavior is unpredictable if this is not done.

Area sizes are encoded as shown in Table 2.18.

Table 2.18. Area size encoding

Bit encoding

Area size

00000 to 01010

Reserved (UNP)

01011

4KB

01100

8KB

01101

16KB

01110

32KB

01111

64KB

10000

128KB

10001

256KB

10010

512KB

10011

1MB

10100

2MB

10101

4MB

10110

8MB

10111

16MB

11000

32MB

11001

64MB

11010

128MB

11011

256MB

11100

512MB

11101

1GB

11110

2GB

11111

4GB

Example base setting

An 8KB size region aligned to an 8KB boundary at 0x0000 2000 (covering the address range 0x0000 2000 to 0x0000 3FFF) is programmed as 0x0000 2019.

The following instruction is supported for backward compatibility with other ARM processors using a memory protection unit.

MRC p15, 0, rd, c6, CRm, 1; returns protection region register

This instruction allows the protection region registers to be read.

Writes to the protection region/base size registers with opcode_2 set to 1 are unpredictable.

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