3.1. Cache architecture

The ARM946E-S incorporates ICache and DCache. You can tailor the size of these to suit individual applications. A range of different cache sizes is supported:

You can select the ICache and DCache sizes independently.

The ICache and DCache are formed from synchronous SRAM, and have similar architectures. An example 8K cache is shown in Figure 3.1.

Figure 3.1. Example 8K cache

The ICache and DCache are four-way set associative, with a cache line length of 8 words (32 bytes). Each cache supports single-cycle read access.

Each cache segment consists of a TAG RAM for storing the cache line address and a data RAM for storing the instructions or data.

During a cache access, all TAG RAMs are accessed for the first nonsequential access, and the TAG address compared with the access address. If a match (or hit) occurs, the data from the segment is selected for return to the ARM9E-S core. If none of the TAGs match (a miss), then external memory must be accessed, unless the access is a buffered write when the write buffer is used.

If a read access from a cachable memory region misses, new data is loaded into one of the four segments. This is an allocate on read miss replacement policy. Selection of the segment is performed by a segment counter that can be clocked in a pseudo-random manner, or in a predictable manner based on the replacement algorithm selected.

Critical or frequently accessed instructions or data can be locked into the cache by restricting the range of the replacement counter. You cannot replace locked lines. They remain in the cache until they are unlocked or flushed.

The access address from the ARM9E-S core can be split into four distinct segments:

The size of the index and address TAGs vary depending on the implemented cache size. Table 3.1 shows how the index and TAG sizes change for the cache sizes supported by the ARM946E-S.

Table 3.1. TAG and index fields for supported cache sizes

Cache size

Index

TAG

4KB

Addr[9:5]

Addr[31:10]

8KB

Addr[10:5]

Addr[31:11]

16KB

Addr[11:5]

Addr[31:12]

32KB

Addr[12:5]

Addr[31:13]

64KB

Addr[13:5]

Addr[31:14]

128KB

Addr[14:5]

Addr[31:15]

256KB

Addr[15:5]

Addr[31:16]

512KB

Addr[16:5]

Addr[31:17]

1MB

Addr[17:5]

Addr[31:18]

For example, the access address is broken down as shown in Figure 3.2 for a 4Kbyte cache.

Figure 3.2. Access address for a 4KB cache

Three additional bits are associated with each TAG entry:

Valid bit

This is set when the cache line has been written with valid data. Only a valid line can return a hit during a cache lookup. On reset, all the valid bits are cleared.

Dirty bits

These are associated with write operations in the DCache and are used to indicate that a cache line contains data that differs from data stored at the address in external memory.

Data can only be marked as dirty if it resides in a write back protection region.

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