3.3. DCache

The ARM946E-S has a four-way set-associative DCache. You can choose the size of the DCache from any of the supported cache sizes. The DCache uses the physical address generated by the processor core. It uses an allocate on read-miss policy, and is always reloaded one cache line (eight words) at a time, through the external interface.

The DCache supports both write back (WB) and write through (WT) modes. For data stores that hit in the DCache, in WB mode the cache line is updated and the dirty bit associated with the half cache line updated is set. This indicates that the internal version of the data differs from that in external memory. In WT mode, a store that hits in the DCache causes the cache line to be updated but not masked as dirty, as the data store is also written to the write buffer to keep the external memory consistent. In both WB and WT modes, a store that misses in the cache is sent to the write buffer. When a linefetch causes a cache line to be evicted from the DCache, the dirty bit for each half of the victim line is read and, if the half-line contains valid and dirty data, it is written back to the write buffer before the linefill replaces it.

The Cachable data (Cd) and Bufferable data (Bd) bits control the behavior of the DCache. For this reason the protection unit must be enabled when the DCache is enabled.

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