ARM ® 946E-S TechnicalReference Manual

Table of Contents

About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback on the ARM946E-S
Feedback on the document
1. Introduction
1.1. About the ARM946E-S
1.2. Microprocessor block diagram
2. Programmer’s Model
2.1. About the ARM946E-S programmer’s model
2.2. About the ARM9E-S programmer’s model
2.2.1. Data Abort model
2.3. CP15 register map summary
2.3.1. Accessing CP15 registers
2.3.2. Register 0, ID code register
2.3.3. Register 0, Cache type register
2.3.4. Register 0, Tightly-coupled memorysize register
2.3.5. Register 1, Control register
2.3.6. Register 2, Cache configuration registers
2.3.7. Register 3, Write buffer control register
2.3.8. Register 5, Access permission registers
2.3.9. Register 6, Protection region/basesize registers
2.3.10. Register 7, Cache operations register
2.3.11. Register 9, Cache lockdown registers
2.3.12. Register 9, Tightly-coupled memoryregion registers
2.3.13. Register 13, Trace process identifier register
2.3.14. Register 15, RAM and TAG BIST testregisters
2.3.15. Register 15, Test state register
2.3.16. Register 15, Cache debug index register
3. Caches
3.1. Cache architecture
3.2. ICache
3.2.1. Enabling and disabling the ICache
3.2.2. ICache operation
3.2.3. ICache validity
3.3. DCache
3.3.1. Enabling and disabling the DCache
3.3.2. Operation of the Bd and Cd bits
3.3.3. DCache operation
3.3.4. DCache validity
3.3.5. DCache clean and flush
3.4. Cache lockdown
3.4.1. Locking down the caches
4. Protection Unit
4.1. About the protection unit
4.1.1. Enabling the protection unit
4.2. Memory regions
4.2.1. Region base address
4.2.2. Region size
4.2.3. Partition attributes
4.3. Overlapping regions
4.3.1. Background regions
5. Tightly-coupled SRAM
5.1. ARM946E-S SRAM requirements
5.2. Using CP15 control register
5.2.1. Enabling the I-SRAM
5.2.2. Disabling the I-SRAM
5.2.3. I-SRAM load mode
5.2.4. Enabling the D-SRAM
5.2.5. Disabling the D-SRAM
5.2.6. D-SRAM load mode
6. Bus Interface Unit and Write Buffer
6.1. About the BIU and write buffer
6.2. AHB bus master interface
6.2.1. About the AHB
6.2.2. ARM946E-S transfer descriptions
6.2.3. Burst sizes
6.2.4. Linefetch transfers
6.2.5. Back to back linefetches
6.2.6. Uncached transfers
6.2.7. Burst accesses
6.2.8. Bursts crossing 1KB boundary
6.3. Noncached Thumb instruction fetches
6.4. AHB clocking
6.4.1. CLK to HCLK skew
6.5. The write buffer
6.5.1. Write buffer operation
6.5.2. Enabling and disabling the write buffer
6.5.3. Self-modifying code
7. Coprocessor Interface
7.1. About the coprocessor interface
7.1.1. Coprocessor instructions
7.2. LDC/STC
7.2.1. Coprocessor handshake states
7.2.2. Coprocessor handshake encoding
7.2.3. Multiple external coprocessors
7.3. MCR/MRC
7.4. Interlocked MCR
7.5. CDP
7.6. Privileged instructions
7.7. Busy-waiting and interrupts
8. Debug Support
8.1. About the debug interface
8.1.1. Debug clocks
8.2. Debug systems
8.2.1. The debug host
8.2.2. The protocol converter
8.2.3. ARM946E‑S debug target
8.3. The JTAG state machine
8.3.1. Reset
8.3.2. Pull-up resistors
8.3.3. Instruction register
8.3.4. Public instructions
8.4. Scan chains
8.4.1. Scan chain 1
8.4.2. Scan chain 2
8.4.3. Scan chain 3
8.4.4. Scan chain 15
8.5. Debug access to the caches
8.5.1. Step 1
8.5.2. Step 2
8.6. Debug interface signals
8.6.1. Entry into debug state on breakpoint
8.6.2. Breakpoints and exceptions
8.6.3. Watchpoints
8.6.4. Watchpoints and exceptions
8.6.5. Debug request
8.6.6. Actions of the ARM9E‑S in debug state
8.7. ARM9E‑S core clock domains
8.8. Determining the core and system state
8.9. Overview of EmbeddedICE-RT
8.10. Disabling EmbeddedICE-RT
8.11. The debug communications channel
8.11.1. Debug comms channel registers
8.11.2. Debug comms channel status register
8.11.3. Debug status register
8.11.4. Communications using the comms channel
8.12. Real-time debug
8.12.1. Further reading - debug in depth
9. ETM Interface
9.1. About the ETM interface
9.2. Enabling the ETM interface
10. Test Support
10.1. About the ARM946E-S test methodology
10.2. Scan insertion and ATPG
10.2.1. ARM946E-S INTEST wrapper
10.3. BIST of memory arrays
10.3.1. BIST control register
10.3.2. BIST address and general registers
10.3.3. Pause modes
A. AC Parameters
A.1. Timing diagrams
A.2. AC timing parameter definitions
B. Signal Descriptions
B.1. Signal properties and requirements
B.2. Clock interface signals
B.3. AHB signals
B.4. Coprocessor interface signals
B.5. Debug signals
B.6. JTAG signals
B.7. Miscellaneous signals
B.8. ETM interface signals
B.9. INTEST wrapper signals

List of Figures

1. Key to timing diagram conventions
1.1. ARM946E-S block diagram
2.1. CP15 MRC and MCR bit pattern
2.2. Index and segment format
2.3. ICache address format
2.4. Process ID format
2.5. Index/segment format
2.6. Data format TAG read/write operations
3.1. Example 8K cache
3.2. Access address for a 4KB cache
3.3. Register 7, Rd format
3.4. Equation for calculating N
4.1. ARM946E-S protection unit
4.2. Overlapping memory regions
5.1. SRAM read cycle
6.1. Linefetch transfer
6.2. Back to back linefetches
6.3. Nonsequential uncached accesses
6.4. Data burst followed by instructionfetch
6.5. Crossing a 1KB boundary
6.6. AHB clock relationships
6.7. ARM946E-S CLK to AHB HCLK sampling
7.1. Coprocessor clocking
7.2. LDC/STC cycle timing
7.3. MCR/MRC transfer timing with busy-wait
7.4. Interlocked MCR/MRC timing with busy-wait
7.5. Late cancelled CDP
7.6. Privileged instructions
7.7. Busy-waiting and interrupts
8.1. Clock synchronization
8.2. Typical debug system
8.3. ARM9E‑S block diagram
8.4. Test access port (TAP) controllerstate transitions
8.5. TAG address format
8.6. Cache index register format
8.7. Breakpoint timing
8.8. Watchpoint entry with data processinginstruction
8.9. Watchpoint entry with branch
8.10. The ARM9E‑S, TAP controller, andEmbeddedICE-RT
8.11. Debug comms channel status register
8.12. Coprocessor 14 debug status registerformat
9.1. ARM946E-S ETM interface
A.1. Clock, reset, and AHB enable timing
A.2. AHB bus request and grant relatedtiming
A.3. AHB bus master timing
A.4. Coprocessor interface timing
A.5. Debug interface timing
A.6. JTAG interface timing
A.7. DBGSDOUT to DBGTDO timing
A.8. Exception and configuration timing
A.9. INTEST wrapper timing
A.10. ETM interface timing

List of Tables

1.1. Location of block descriptions
2.1. CP15 register map
2.2. CP15 abbreviations
2.3. Register 0, ID code
2.4. Cache type register format
2.5. Cache size encoding
2.6. Cache associativity encoding
2.7. Tightly-coupled memory size register
2.8. Memory size field
2.9. Register 1, control register
2.10. Programming instruction/data cachable bits
2.11. Programming data bufferable bits
2.12. Programming instruction and data access permission bits (extended)
2.13. Access permission encoding (extended)
2.14. Instruction and data access permission bits (standard)
2.15. Access permission encoding (standard)
2.16. Accessing protection region/base size registers
2.17. Protection region/base size register format
2.18. Area size encoding
2.19. Cache operations
2.20. Index fields for supported cache sizes
2.21. Lockdown register format
2.22. Protection region/base size register format
2.23. Tightly-coupled memory area size encoding
2.24. Register 15, BIST instructions
2.25. Register 15, implementation-specific BIST instructions
2.26. Test state register bit assignments
2.27. Additional operations
2.28. Index fields for supported cache sizes
3.1. TAG and index fields for supported cache sizes
3.2. Meaning of Cd bit values
3.3. Calculating index addresses
4.1. Protection register format
4.2. Region size encoding  
6.1. Supported burst types
6.2. Data write modes
7.1. Handshake encoding
8.1. Public instructions
8.2. ARM946E-S scan chain allocations
8.3. Scan chain 1 bits
8.4. Scan chain 15 addressing mode bit order
8.5. Mapping of scan chain 15 address field to CP15 registers
8.6. Coprocessor 14 register map
10.1. Instruction BIST address and general registers
10.2. Data BIST address and general registers
A.1. Timing parameter definitions
B.1. Clock interface signals
B.2. AHB signals
B.3. Coprocessor interface signals
B.4. Debug signals
B.5. JTAG signals
B.6. Miscellaneous signals
B.7. ETM interface signals
B.8. INTEST wrapper signals

Proprietary Notice

ARM, the ARM Powered logo, Thumb and StrongARM are registeredtrademarks of ARM Limited.

The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen,Multi-ICE, PrimeCell, ARM7TDMI, ARM7TDMI‑S, ARM9TDMI, ARM9E-S, ARM946E-S,ARM966E-S, ETM7, ETM9, TDMI, and STRONG are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties or merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Figure 8.4 reprintedwith permission IEEE Std 1149.1-1990, IEEE Standard Test AccessPort and Boundary-Scan Architecture Copyright2000, by IEEE. TheIEEE disclaims any responsibility or liability resulting from theplacement and use in the described manner.

Confidentiality Status

This document is Open Access. This means there is no restrictionon the distribution of information.


The information in this document is Final (information ona developed product).

Revision History
Revision A 11thAugust 2000 First release
Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0155A