Using this manual

This document is organized into the following chapters:

Chapter 1 Introduction

This chapter provides an introduction to the ARM946E-S.

Chapter 2 Programmer’s Model

This chapter describes the programmer’s model of the ARM946E-S and includes a summary of the ARM946E-S coprocessor registers.

Chapter 3 Caches

This chapter describes the ARM946E-S cache implementation.

Chapter 4 Protection Unit

This chapter describes the ARM946E-S protection unit.

Chapter 5 Tightly-coupled SRAM

This chapter describes the requirements and operation of the tightly-coupled SRAM.

Chapter 6 Bus Interface Unit and Write Buffer

This chapter describes the operation of the Bus Interface Unit and write buffer.

Chapter 7 Coprocessor Interface

This chapter describes the coprocessor interface and the operation of common coprocessor instructions.

Chapter 8 Debug Support

This chapter describes the debug support for the ARM946E-S and the EmbeddedICE-RT logic.

Chapter 9 ETM Interface

This chapter describes the ETM interface, including details of how to enable the interface.

Chapter 10 Test Support

This chapter describes the test methodology used for the ARM946E-S synthesized logic and tightly-coupled SRAM.

Appendix A AC Parameters

This appendix describes the timing parameters applicable to the ARM946E-S.

Appendix B Signal Descriptions

This appendix describes the signals used in the ARM946E-S.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
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