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Figure 4‑2 shows a memory map decode example based on an ARM966E-S system.
The combinational logic used to decode memory map addresses in Figure 4‑2 on page 4‑4 is shown in pseudo-HDL format in Table 4‑1.
Table 4.1. Memory map decode example pseudo-HDL
| Logic expression | Comment |
|---|---|
| MMDIN[0] = (MMDIA[31:24] = 0x00) AND NOT(MMDInMREQ) | I-SRAM |
| MMDIN[1] = (MMDIA[31:24] = 0x04) AND NOT(MMDInMREQ) | D-SRAM |
| MMDIN[2] = (MMDDA[31:24] = 0x08) AND NOT(MMDDnMREQ) | Data access to flash |
| MMDIN[3] = (MMDIA[31:24] = 0x08) AND NOT(MMDInMREQ) | Instruction access to flash |
| MMDIN[4] = (MMDDA[31:20] = 0x100) AND NOT(MMDDnMREQ) | Three unbuffered peripherals |
| MMDIN[5] = (MMDDA[31:20] = 0x101) AND NOT(MMDDnMREQ) | |
| MMDIN[6] = (MMDDA[31:20] = 0x102) AND NOT(MMDDnMREQ) | |
| MMDIN[7] = (MMDDA[31:20] = 0x200) AND NOT(MMDDnMREQ) | Two buffered peripherals |
| MMDIN[8] = (MMDDA[31:20] = 0x201) AND NOT(MMDDnMREQ) | |
| MMDIN[9] = (MMDDA[31:28] = 0x4) AND NOT(MMDDnMREQ) | Off-chip SDRAM |
| MMDIN[10] = (MMDDA[31:28] = 0x600) AND NOT(MMDDnMREQ) | Off-chip buffered peripherals |
| MMDIN[11] = (MMDDA[31:28] = 0x601) AND NOT(MMDDnMREQ) | |
| MMDIN[12] = (MMDDA[31:28] = 0x602) AND NOT(MMDDnMREQ) | |
| MMDIN[13] = (MMDDA[31:28] = 0x603) AND NOT(MMDDnMREQ) | |
| MMDIN[14] = (MMDDA[31:28] = 0x604) AND NOT(MMDDnMREQ) |