ETM9™ Technical Reference Manual 3.2.1. ETM9 to ARM9 connection guide

3.2.1. ETM9 to ARM9 connection guide

The ETM9 port names are a mixture of those from the ARM9TDMI, ARM9E-S, and ARM9EJ-S macrocells.

Table 3.1 and Table 3.2 show how the ETM9 must be connected to different members of the ARM9 processor family.

Table 3.1 shows ETM9 connections for the following macrocells:

ARM9E-S
ARM9TDMI
ARM920T (Rev 1)
ARM922T
the generic trace interface on ARM946E-S and ARM966E-S.

Note

The ARM966E-S connections shown in Table 3.1 are for a (Rev 1) ARM966E-S (Rev 1) processor. If you are using a ARM966E-S (Rev 0) processor, you must tie off the unused ETM9 inputs as described in the following sections:
- INSTRVALID
- Using the context ID signals.
The connections for the ARM922T (Rev 0) and ARM920T (Rev 1) processors are identical.
The External Inputs EXTIN[3:0] must be synchronous to the ETM9 CLK

Table 3.1. Signal connections between ETM9 and ARM9 cores without Jazelle extensions

ETM9 signal name	ARM processor signal name
ETM9 signal name	ARM9E-S	ARM9TDMI	ARM920T (Rev 1) and ARM922T	ARM946E-S and ARM966E-S (Rev 1) (generic trace interface)
ARMTDO ^[1]	-	-	-	-
BIGEND	CFGBIGEND	BIGEND	ETMBIGEND	ETMBIGEND
CHSD[1:0]	CHSD[1:0]	CHSD[1:0]	ETMCHSD[1:0]	ETMCHSD[1:0]
CHSE[1:0]	CHSE[1:0]	CHSE[1:0]	ETMCHSE[1:0]	ETMCHSE[1:0]
CLK ^[2]^c	CLK	GCLK	ETMCLOCK	CLK
CLKEN ^[3]	CLKEN	nWAIT	ETMnWAIT	ETMnWAIT
DA[31:0]	DA[31:0]	DA[31:0]	ETMDA[31:0]	ETMDA[31:0]
DABORT	DABORT	DABORT	ETMDABORT	ETMDABORT
DBGACK	DBGACK	DBGACK	ETMDBGACK	ETMDBGACK
DBGRQ ^[4]	EDBGRQ	EDBGRQ	EDBGRQ	EDBGRQ
DD[31:0]	WDATA[31:0]	DD[31:0]	ETMDD[31:0]	ETMWDATA[31:0]
DDIN[31:0]	RDATA[31:0]	DDIN[31:0]	ETMDD[31:0]	ETMRDATA[31:0]
DMAS[1:0]	DMAS[1:0]	DMAS[1:0]	ETMDMAS[1:0]	ETMDMAS[1:0]
DnMREQ	DnMREQ	DnMREQ	ETMDnMREQ	ETMDnMREQ
DnRW	DnRW	DnRW	ETMDnRW	ETMDnRW
DSEQ	DSEQ	DSEQ	ETMDSEQ	ETMDSEQ
ETMEN ^[5]	-	-	-	-
FIFOFULL	-	-	-	FIFOFULL ^[6]
HIVECS	CFGHIVECS	HIVECS	ETMHIVECS	ETMHIVECS
IA[0] ^[7]	GND	GND	GND	GND
IA[31:1]	IA[31:1]	IA[31:1]	ETMIA[31:1]	ETMIA[31:1]
ID15To11[15:11]	INSTR[15:11]	ID[15:11]	ETMID15To8[15:11]	ETMID15To8[15:11]
ID31To25[31:25]	INSTR[31:25]	ID[31:25]	ETMID31To24[31:25]	ETMID31To24[31:25]
IJBIT^g	GND	GND	GND	GND
InMREQ	InMREQ	InMREQ	ETMInMREQ	ETMInMREQ
INSTREXEC	DBGINSTREXEC	INSTREXEC	ETMINSTREXEC	ETMINSTREXEC
INSTRVALID	DBGINSTRVALID	V_DD	V_DD	ETMINSTRVALID
ISEQ	ISEQ	ISEQ	ETMISEQ	ETMISEQ
ITBIT	ITBIT	ITBIT	ETMITBIT	ETMITBIT
LATECANCEL	LATECANCEL	LATECANCEL	ETMLATECANCEL	ETMLATECANCEL
nRESET ^[8]	DBGnTRST	nTRST	nTRST	DBGnTRST
nTRST	DBGnTRST	nTRST	nTRST	DBGnTRST
PASS	PASS	PASS	ETMPASS	ETMPASS
PROCID[31:0]	-	-	-	ETMPROCID[31:0]
PROCIDWR	-	-	-	ETMPROCIDWR
PWRDOWN ^[9]	-	-	ETMPWRDOWN	!ETMEN^e
RANGEOUT[0]	DBGRNG[0]	RANGEOUT[0]	ETMRNGOUT[0]	ETMRNGOUT[0]
RANGEOUT[1]	DBGRNG[1]	RANGEOUT[1]	ETMRNGOUT[1]	ETMRNGOUT[1]
TCK	CLK	TCK	TCK	CLK
TCKEN	DBGTCKEN	V_DD	V_DD	DBGTCKEN
TDI	DBGTDI	TDI	TDI	DBGTDI
TDO	DBGSDOUT	SDOUTBS	SDOUTBS	DBGSDOUT
TMS	DBGTMS	TMS	TMS	DBGTMS
ZIFIRST ^g	GND	GND	GND	GND
ZILAST ^g	GND	GND	GND	GND
^[1]See TAP interface wiring. ^[2]See Trace signal output timing. ^[3]See CLK and CLKEN. ^[4]See Debug request output wiring. ^[5]In cores supporting the generic trace interface, the ETMEN input to the core must be connected to an inverted version of PWRDOWN. The ETMEN output is not connected to the core. ^[6]In revisions where FIFOFULL is supported. ^[7]See Memory interface signals on ETM9 (Rev 2 and above). ^[8]See Clocks and resets. ^[9]See Using the PWRDOWN output.

Table 3.2 shows ETM9 connections for:

ARM9EJ-S cores
the generic trace interface on ARM926EJ-S.

Table 3.2. ETM9 and Jazelle-enabled ARM9 cores signal connections

ETM9 signal name	ARM processor signal name
ETM9 signal name	ARM9EJ-S	ARM926EJ-S (generic trace interface)
ARMTDO ^[1]	-	-
BIGEND	CFGBIGEND	ETMBIGEND
CHSD[1:0]	CHSD[1:0]	ETMCHSD[1:0]
CHSE[1:0]	CHSE[1:0]	ETMCHSE[1:0]
CLK ^[2]^c	CLK	CLK
CLKEN ^[3]	CLKEN	ETMnWAIT
DA[31:0]	DA[31:0]	ETMDA[31:0]
DABORT	DABORT	ETMDABORT
DBGACK	DBGACK	ETMDBGACK
DBGRQ ^[4]	EDBGRQ	EDBGRQ
DD[31:0]	WDATA[31:0]	ETMWDATA[31:0]
DDIN[31:0]	RDATA[31:0]	ETMRDATA[31:0]
DMAS[1:0]	DMAS[1:0]	ETMDMAS[1:0]
DnMREQ	DnMREQ	ETMDnMREQ
DnRW	DnRW	ETMDnRW
DSEQ	DSEQ	ETMDSEQ
ETMEN ^[5]	-	-
FIFOFULL	-	FIFOFULL
HIVECS	CFGHIVECS	ETMHIVECS
IA[0] ^[6]	IA[0]	ETMIA[0]
IA[31:1]	IA[31:1]	ETMIA[31:1]
ID15To11[15:11]	INSTR[15:11]	ETMID15To8[15:11]
ID31To25[31:25]	INSTR[31:25]	ETMID31To24[31:25]
IJBIT ^f	IJBIT	ETMIJBIT
InMREQ	InMREQ	ETMInMREQ
INSTREXEC	DBGINSTREXEC	ETMINSTREXEC
INSTRVALID	DBGINSTRVALID	ETMINSTRVALID
ISEQ	ISEQ	ETMISEQ
ITBIT	ITBIT	ETMITBIT
LATECANCEL	LATECANCEL	ETMLATECANCEL
nRESET ^[7]	DBGnTRST	DBGnTRST
nTRST	DBGnTRST	DBGnTRST
PASS	PASS	ETMPASS
PROCID[31:0]	-	ETMPROCID[31:0]
PROCIDWR	-	ETMPROCIDWR
PWRDOWN ^[8]	-	!ETMEN^e
RANGEOUT[0]	DBGRNG[0]	ETMRNGOUT[0]
RANGEOUT[1]	DBGRNG[1]	ETMRNGOUT[1]
TCK	CLK	CLK
TCKEN	DBGTCKEN	DBGTCKEN
TDI	DBGTDI	DBGTDI
TDO	DBGSDOUT	DBGSDOUT
TMS	DBGTMS	DBGTMS
ZIFIRST ^f	ZIFIRST	ETMZIFIRST
ZILAST ^f	ZILAST	ETMZILAST
^[1]See TAP interface wiring. ^[2]See Trace signal output timing. ^[3]See CLK and CLKEN. ^[4]See Debug request output wiring. ^[5]In cores supporting the generic trace interface, the ETMEN input to the core must be connected to an inverted version of PWRDOWN. The ETMEN output is not connected to the core. ^[6]See Memory interface signals on ETM9 (Rev 2 and above). ^[7]See Clocks and resets. ^[8]See Using the PWRDOWN output.

Note

Earlier revisions of ETM9 (Rev 0a and below) also included the DMORE signal. This signal is no longer required.

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