| CLK, CLKEN, nRESET | If any of these are not correctly connected,
the test fails at either runtime or during test verification. |
| TCK, TCKEN, TDI, TDO, TMS, nTRST | If any of these are not correctly connected,
the test fails at either runtime or during test verification. In
ARM926EJ-S, ARM946E-S and ARM966E-S-based systems, TCKEN is generated by a Linear
Feedback Shift Register (LFSR) to ensure the connection
is correct. |
| ARMTDO | This pin is not directly tested. It must be
tested if an external scan chain is connected to the ETM. This may
be performed by reading some data from the external scan chain using
the JTAG interface. |
| DA[31:0], DD[31:0], DDIN[31:0], DnMREQ, DSEQ, DnRW, DMAS[1:0], IA[31:0], ID31To25[31:25], ID15To11[15:11], InMREQ, ISEQ, INSTREXEC | These are tested by performing multiple memory
accesses. If incorrectly connected, the test verification indicates incorrect
data. |
| DABORT | This pin is not directly tested. It is used
by the ETM to control data comparator behavior, and cannot easily
be tested. |
| ITBIT | This bit is tested by switching between ARM
and Thumb state. Test verification indicates incorrect transitions
if this is incorrectly connected. |
| IJBIT, ZIFIRST, ZILAST | These pins are tested by switching between
ARM and Java state. Test verification indicates incorrect transitions
if this is incorrectly connected. This is only tested on an ARM926EJ-S
core because it supports Java. They are not tested on ARM920T, ARM922T,
ARM946E-S, or ARM966E-S cores and must be tied LOW. |
| INSTRVALID | This pin is not directly tested. It is used
to increase the accuracy of timing at the point an interrupt is
taken, and cannot be easily tested. The ARM920T or ARM922T cores do
not support this signal. |
| CHSD[1:0], CHSE[1:0] | These coprocessor signals are tested by transferring
data to and from a coprocessor. Test verification indicates if these are
incorrectly connected by not tracing coprocessor instructions properly. |
| LATECANCEL | This coprocessor signal is tested by causing
a Data Abort in the instruction preceding a coprocessor instruction.
If it is connected incorrectly, this is indicated during test verification. |
| PASS | If this is not correctly connected, the test
fails during test verification. |
| DBGRQ, DBGACK | These debug signals are tested by asserting DBGRQ to send the core into debug,
and checking DBGACK is asserted
in response. If any of these are not correctly connected, the test
may fail at either run time or during test verification. |
| RANGEOUT[1:0] | These are tested by activating the EmbeddedICE watchpoint
units within the ARM core. If any of these are not correctly connected,
the test fails at runtime. |
| BIGEND, HIVECS | If these pins are connected incorrectly, this
is indicated during test verification. |
| PROCID[31:0], PROCIDWR | These are tested by toggling all the bits in
the Process ID register. If any of these are not correctly connected,
this is indicated during test verification. |
| PIPESTAT[2:0], TRACEPKT[15:0], TRACESYNC | These trace port signals are tested by analyzing
the trace output. If any of these are not correctly connected, this
is indicated during test verification. |
| PWRDOWN | This is used to gate the CLK input
to the ETM. If this is not correctly connected, the test fails at
either runtime or during test verification. |
| ETMEN | This is tested by the test bench and the test
program. If this is not correctly connected, the test fails at either
runtime or during test verification. |
| PORTMODE[1:0], CLKDIVTWOEN | The ETMMuxDemux module incorrectly
formats the data if these signals are incorrectly connected. If
any of these are not correctly connected, this is indicated during
test verification. |
| PORTSIZE[2:0] | These are only tested when using the ETB. If
incorrectly connected, this is indicated during test verification.
If not using the ETB, the use of PORTSIZE is
implementation defined. This pin is not tested by the test program. |
| FIFOFULL | This is tested by enabling FIFOFULL stalling
on the ETM9. This signal is not tested on the ARM920T or ARM922T
cores, because they do not support FIFOFULL stalling. If it is incorrectly
connected, ETM FIFO overflow occurs. See Running the Trace Comparison Script for details on how to check if FIFO overflow
has occurred. |
| MMDA[31:0], MMDn, MREQ, MMDnRW, MMDnOPC, MMDMAS[1:0], MMDCTRL[7:0], MMDIN[15:0], EXTOUT[3:0], EXTIN[3:0] | These are external signals whose use is implementation-defined.
They are not tested by the test program, but must be tested if you
intend to use these connections. Appropriate locations for these
modifications are indicated in the test program. |
| SYSOPT[7:0] | The test program reads the ETM System Configuration register
through the JTAG port to verify it is connected as expected. If
this is not correctly connected, the test fails at run time. The
file log.dsm_bst indicates the stage at which the
test failed. |
| WSI, WSO, MUXINSEL, MUXOUTSEL, WSEI, WSEO, WEDGE, SCANMODE | These are Design For Test signals whose use
is implementation defined. They are not directly tested by the test
programs, but must be tested if you intend to use these connections. |
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