ETM9 ™ Technical ReferenceManual

Revision: r2p2

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ETM9 ™ Technical ReferenceManual

Revision: r2p2

Copyright © 1999-2002, 2006 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this document

Intended audience
Product revision status
Using this manual
Typographical conventions
Timing diagram conventions
Further reading

Feedback on the ETM9
Feedback on this book

1. Introduction

1.1. About the ETM9

1.2. Product revisions

1.2.1. ETM versions and variants
1.2.2. Pin names
1.2.3. Changes to the programmer’s modelin Rev 0a
1.2.4. Changes to the programmer’s modelin Rev 1
1.2.5. Changes to the programmer’s modelin Rev 2
1.2.6. Changes to the programmer’s modelin Rev 2a
1.2.7. Changes to the programmer’s modelin r2p2

2. Accessing ETM9 Registers

2.1. TAP interface
2.2. Programming and reading ETM9 registers

3. Integrating the ETM9

3.1. About integrating the ETM9

3.2. ARM interfacing

3.2.1. ETM9 to ARM9 connection guide
3.2.2. INSTRVALID
3.2.3. Data buses
3.2.4. Coprocessor data bus connections
3.2.5. Memory interface signals on ETM9 (Rev2 and above)

3.3. Clocks and resets

3.3.1. CLK and CLKEN
3.3.2. ETM reset
3.3.3. TCK and TCKEN
3.3.4. TAP reset

3.4. TAP interface wiring

3.4.1. IEEE 1149.1 compatibility
3.4.2. Multiprocessor TAP structure

3.5. System control signals

3.5.1. Debug request output wiring
3.5.2. Using the PWRDOWN output
3.5.3. FIFOFULL
3.5.4. Using the context ID signals
3.5.5. Using the system options bus

3.6. Trace port interfacing

3.6.1. Trace port logic
3.6.2. Single-processor tracing
3.6.3. Dual-processor tracing
3.6.4. Trace signal output timing
3.6.5. PCB design guidelines

3.7. Modes of operation of the trace port

3.7.1. Normal trace port signals
3.7.2. Multiplexed trace port signals
3.7.3. Demultiplexed trace port signals
3.7.4. Operation with asynchronous TCK

4. Memory Map Decode Interface

4.1. About the memory map decode interface

4.1.1. Signal descriptions

4.2. Memory map decode example

5. Test Wrapper

5.1. About the ETM9 test wrapper

5.1.1. Scan insertion and ATPG

6. ETM Integration Testing

6.1. About the ETM Integration Kit

6.1.1. Design flow
6.1.2. Supported configurations
6.1.3. Directory structure
6.1.4. Additional components required
6.1.5. Design structure

6.2. Test system

6.2.1. The system test bench
6.2.2. HDL hierarchy

6.3. ETM integration test program

6.3.1. Test program breakdown
6.3.2. Adapting the test program

6.4. Trace buffer integration test program

6.5. Simple demonstration test

6.6. Source compilation

6.6.1. Environment set up
6.6.2. Verilog source compilation
6.6.3. Test program compilation

6.7. Simulation

6.7.1. Analyzing the ETM integration test simulation results
6.7.2. Analyzing the ETB Integration test simulation results

6.8. Test verification

6.8.1. Trace Comparison Scripts
6.8.2. Decompressor
6.8.3. Executed Instruction Stream converter
6.8.4. Trace Buffer Extraction Script
6.8.5. ETM Port Mode Conversion Script
6.8.6. EtmCompare

6.9. Running the Trace Comparison Script

6.10. Troubleshooting

6.10.1. Log files
6.10.2. EtmCompare Errors
6.10.3. Information messages

7. Software Considerations for Trace

7.1. Tracing dynamically loaded images

7.1.1. Why dynamically-loaded code requires special hardwareand software support
7.1.2. ETM9 (Rev 1 and above) hardware support

7.2. Simple overlay support

7.2.1. Overlay support on ARM926EJ-S, ARM946E-S, and ARM966E-Smacrocells

8. Physical Trace Port Signal Guidelines

8.1. About trace port signal quality

8.2. ASIC pad selection, placement, andpackage type

8.3. PCB design guidelines

8.3.1. Dedicated trace port
8.3.2. Shared trace port

8.4. EMI compliance

8.5. Further references

A. Signal Descriptions

A.1. Signal descriptions

B. Integrating the EtmMuxDemux Block into ETM9

B.1. Using the EtmMuxDemux block

List of Figures

1. Key to timing diagram conventions
1.1. Block diagram of the ETM9
1.2. Signal diagram
2.1. ETM9 TAP structure
3.1. Coprocessor databus connections
3.2. Synchronizingreset
3.3. TAP interfacestructure
3.4. Using ETM9 andARM9 with an external scan chain
3.5. TDO output retiming for IEEE 1149.1compatibility
3.6. MultiprocessorTAP structure
3.7. Combining DBGRQinputs
3.8. Clock gating theETM9
3.9. Connecting PWRDOWN to cores thatdo not support the generic trace interface
3.10. Connecting PWRDOWN to cores thatsupport the generic trace interface
3.11. Change in Context ID
3.12. Trace output circuitwith inverted clock
3.13. Trace output circuitusing falling-edge D-types
3.14. Multiplexing datatrace signals
3.15. Multiplexed signal timing
3.16. Demultiplexing trace data signals
3.17. Demultiplexed signal timing
4.1. Memory map decode logic structure
4.2. Memory map decode example based on an ARM966E-S core
5.1. Scannable registers in ETM9
5.2. Test wrapper
5.3. Testing SoC logic with test wrappers
6.1. ETMIK design flow
6.2. ETMIK directory structure
6.3. Design structure
6.4. HDL hierarchy
6.5. JTAG wiring
7.1. SDRAM example overlays
7.2. Mapping overlays to a physical address
B.1. ETM to EtmMuxDemux connections

List of Tables

1.1. ETM versions and variants
1.2. ETM9 pin names
3.1. Signal connections between ETM9 and ARM9 cores without Jazelleextensions
3.2. ETM9 and Jazelle-enabled ARM9 cores signal connections
3.3. ETMEN and PWRDOWN combinations
3.4. SYSOPT bus settings
3.5. Single-processor configurations
3.6. Dual-processor trace port configurations
3.7. TRACECLK behavior in available modes
3.8. Paired signals in a multiplexed trace port connector
4.1. Memory map decode example pseudo-HDL
5.1. Scan configuration pins
6.1. Additional components
6.2. ETM7 signals
6.3. ETM9 signals
6.4. ETB signals
A.1. ETM9 signals

Proprietary Notice

Words and logos marked with ^® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A	14December 1999	ETM9 (Rev 0) release.
Revision B	28February 2000	ETM9 (Rev 0a) release.
Revision C	6September 2000	ETM9 (Rev 1) release.
Revision D	15January 2001	ETM9 (Rev 2) release to NDA signatoriesonly.
Revision E	6June 2001	ETM9 (Rev 2a) release. Open Access.
Revision F	20August 2002	ETM9 Revision: r2p2.
Revision G	27September 2006	Added content for DFT.

Copyright © 1999-2002, 2006 ARM Limited. All rights reserved.	ARM DDI 0157G
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