5.6. Modifying your ASIC test bench

To test the ETM in your system you must add the BST DSM and the EtmMonitor HDL into your ASIC test bench. You must add these components at the highest possible level to ensure that all of the trace port and JTAG wiring is fully tested. For example you must not add these components inside your ASIC.The BST and the EtmMonitor script provide the same functionality as the run control and TPA hardware that you will use to develop your software.The example test bench shows how the two components should be integrated into a Verilog test bench. Also, the README file provided with the BST tells you how to integrate the BST DSM into your chosen simulator.A VHDL version of the EtmMonitor script is provided in the release.

EtmMonitor.vhd

Contains the entity model.

EtmMonitor-behavioural.vhd

Contains the architectural model.

The test program supports character output and automatic termination of the simulation using a memory-mapped tube. The example test bench implements this at address 0x03000000. Writes to this address are sent to the simulator, and a write of 0x04 terminates the simulation once the ETM FIFO has drained.

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